diff --git a/dts/arm/st/f0/stm32f0.dtsi b/dts/arm/st/f0/stm32f0.dtsi index 162d2d228df..e32e3684235 100644 --- a/dts/arm/st/f0/stm32f0.dtsi +++ b/dts/arm/st/f0/stm32f0.dtsi @@ -293,6 +293,15 @@ #pwm-cells = <2>; }; }; + + adc1: adc@40012400 { + compatible = "st,stm32-adc"; + reg = <0x40012400 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>; + interrupts = <12 0>; + status = "disabled"; + label = "ADC_1"; + }; }; }; diff --git a/dts/arm/st/f1/stm32f1.dtsi b/dts/arm/st/f1/stm32f1.dtsi index 80668f9c847..09b7b566e3e 100644 --- a/dts/arm/st/f1/stm32f1.dtsi +++ b/dts/arm/st/f1/stm32f1.dtsi @@ -227,6 +227,15 @@ #pwm-cells = <2>; }; }; + + adc1: adc@40012400 { + compatible = "st,stm32-adc"; + reg = <0x40012400 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>; + interrupts = <18 0>; + status = "disabled"; + label = "ADC_1"; + }; }; }; diff --git a/dts/arm/st/f2/stm32f2.dtsi b/dts/arm/st/f2/stm32f2.dtsi index 45241a0c620..05059165af8 100644 --- a/dts/arm/st/f2/stm32f2.dtsi +++ b/dts/arm/st/f2/stm32f2.dtsi @@ -213,6 +213,15 @@ status = "disabled"; label = "OTGFS"; }; + + adc1: adc@40012000 { + compatible = "st,stm32-adc"; + reg = <0x40012000 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000100>; + interrupts = <18 0>; + status = "disabled"; + label = "ADC_1"; + }; }; otgfs_phy: otgfs_phy { diff --git a/dts/arm/st/f3/stm32f3.dtsi b/dts/arm/st/f3/stm32f3.dtsi index 6e3461d46ae..9b0ea00c03b 100644 --- a/dts/arm/st/f3/stm32f3.dtsi +++ b/dts/arm/st/f3/stm32f3.dtsi @@ -297,6 +297,15 @@ status = "disabled"; label = "RTC_0"; }; + + adc1: adc@50000000 { + compatible = "st,stm32-adc"; + reg = <0x50000000 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>; + interrupts = <18 0>; + status = "disabled"; + label = "ADC_1"; + }; }; usb_fs_phy: usbphy { diff --git a/dts/arm/st/f4/stm32f4.dtsi b/dts/arm/st/f4/stm32f4.dtsi index cd519c51dbb..209c6ca2fd3 100644 --- a/dts/arm/st/f4/stm32f4.dtsi +++ b/dts/arm/st/f4/stm32f4.dtsi @@ -359,6 +359,15 @@ status = "disabled"; label = "RTC_0"; }; + + adc1: adc@40012000 { + compatible = "st,stm32-adc"; + reg = <0x40012000 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000100>; + interrupts = <18 0>; + status = "disabled"; + label = "ADC_1"; + }; }; otgfs_phy: otgfs_phy { diff --git a/dts/arm/st/f7/stm32f7.dtsi b/dts/arm/st/f7/stm32f7.dtsi index cfe79bd57e4..e53cbb52f1e 100644 --- a/dts/arm/st/f7/stm32f7.dtsi +++ b/dts/arm/st/f7/stm32f7.dtsi @@ -595,6 +595,15 @@ status = "disabled"; label = "RTC_0"; }; + + adc1: adc@40012000 { + compatible = "st,stm32-adc"; + reg = <0x40012000 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000100>; + interrupts = <18 0>; + status = "disabled"; + label = "ADC_1"; + }; }; otghs_fs_phy: otghs_fs_phy { diff --git a/dts/arm/st/l0/stm32l0.dtsi b/dts/arm/st/l0/stm32l0.dtsi index e78f640ed98..c6e0f844f40 100644 --- a/dts/arm/st/l0/stm32l0.dtsi +++ b/dts/arm/st/l0/stm32l0.dtsi @@ -162,6 +162,15 @@ status = "disabled"; label = "SPI_1"; }; + + adc1: adc@40012400 { + compatible = "st,stm32-adc"; + reg = <0x40012400 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>; + interrupts = <12 0>; + status = "disabled"; + label = "ADC_1"; + }; }; }; diff --git a/dts/arm/st/l4/stm32l4.dtsi b/dts/arm/st/l4/stm32l4.dtsi index d1f911d7465..826a15b0ae6 100644 --- a/dts/arm/st/l4/stm32l4.dtsi +++ b/dts/arm/st/l4/stm32l4.dtsi @@ -291,6 +291,15 @@ status = "disabled"; label = "RTC_0"; }; + + adc1: adc@50040000 { + compatible = "st,stm32-adc"; + reg = <0x50040000 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>; + interrupts = <18 0>; + status = "disabled"; + label = "ADC_1"; + }; }; }; diff --git a/dts/bindings/iio/adc/st,stm32-adc.yaml b/dts/bindings/iio/adc/st,stm32-adc.yaml new file mode 100644 index 00000000000..56368338504 --- /dev/null +++ b/dts/bindings/iio/adc/st,stm32-adc.yaml @@ -0,0 +1,41 @@ +# +# Copyright (c) 2018, Endre Karlson +# Copyright (c) 2018, Song Qiang +# +# SPDX-License-Identifier: Apache-2.0 +# +--- +title: ST STM32 family ADC +version: 0.1 + +description: > + This binding gives a base representation of the ST STM32 ADC + +inherits: + !include adc.yaml + +properties: + compatible: + type: string + category: required + description: compatible strings + constraint: "st,stm32-adc" + + reg: + type: array + description: mmio register space + generation: define + category: required + + clocks: + type: array + category: required + description: Clock gate control information + generation: define + + interrupts: + type: array + category: required + description: required interrupts + generation: define +... diff --git a/soc/arm/st_stm32/stm32f0/dts_fixup.h b/soc/arm/st_stm32/stm32f0/dts_fixup.h index ce2df49bd92..8536285016d 100644 --- a/soc/arm/st_stm32/stm32f0/dts_fixup.h +++ b/soc/arm/st_stm32/stm32f0/dts_fixup.h @@ -187,4 +187,11 @@ #define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL +#define DT_ADC_1_BASE_ADDRESS DT_ST_STM32_ADC_40012400_BASE_ADDRESS +#define DT_ADC_1_IRQ DT_ST_STM32_ADC_40012400_IRQ_0 +#define DT_ADC_1_IRQ_PRI DT_ST_STM32_ADC_40012400_IRQ_0_PRIORITY +#define DT_ADC_1_NAME DT_ST_STM32_ADC_40012400_LABEL +#define DT_ADC_1_CLOCK_BITS DT_ST_STM32_ADC_40012400_CLOCK_BITS_0 +#define DT_ADC_1_CLOCK_BUS DT_ST_STM32_ADC_40012400_CLOCK_BUS_0 + /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/st_stm32/stm32f1/dts_fixup.h b/soc/arm/st_stm32/stm32f1/dts_fixup.h index 81cd435f55f..f2ccab53343 100644 --- a/soc/arm/st_stm32/stm32f1/dts_fixup.h +++ b/soc/arm/st_stm32/stm32f1/dts_fixup.h @@ -207,4 +207,11 @@ #define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL +#define DT_ADC_1_BASE_ADDRESS DT_ST_STM32_ADC_40012400_BASE_ADDRESS +#define DT_ADC_1_IRQ DT_ST_STM32_ADC_40012400_IRQ_0 +#define DT_ADC_1_IRQ_PRI DT_ST_STM32_ADC_40012400_IRQ_0_PRIORITY +#define DT_ADC_1_NAME DT_ST_STM32_ADC_40012400_LABEL +#define DT_ADC_1_CLOCK_BITS DT_ST_STM32_ADC_40012400_CLOCK_BITS_0 +#define DT_ADC_1_CLOCK_BUS DT_ST_STM32_ADC_40012400_CLOCK_BUS_0 + /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/st_stm32/stm32f2/dts_fixup.h b/soc/arm/st_stm32/stm32f2/dts_fixup.h index 8be29b46e1b..9bf1c011934 100644 --- a/soc/arm/st_stm32/stm32f2/dts_fixup.h +++ b/soc/arm/st_stm32/stm32f2/dts_fixup.h @@ -148,4 +148,11 @@ #define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL +#define DT_ADC_1_BASE_ADDRESS DT_ST_STM32_ADC_40012000_BASE_ADDRESS +#define DT_ADC_1_IRQ DT_ST_STM32_ADC_40012000_IRQ_0 +#define DT_ADC_1_IRQ_PRI DT_ST_STM32_ADC_40012000_IRQ_0_PRIORITY +#define DT_ADC_1_NAME DT_ST_STM32_ADC_40012000_LABEL +#define DT_ADC_1_CLOCK_BITS DT_ST_STM32_ADC_40012000_CLOCK_BITS_0 +#define DT_ADC_1_CLOCK_BUS DT_ST_STM32_ADC_40012000_CLOCK_BUS_0 + /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/st_stm32/stm32f3/dts_fixup.h b/soc/arm/st_stm32/stm32f3/dts_fixup.h index a4da929fae8..3f24fd9006d 100644 --- a/soc/arm/st_stm32/stm32f3/dts_fixup.h +++ b/soc/arm/st_stm32/stm32f3/dts_fixup.h @@ -263,4 +263,12 @@ #define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL #define DT_RTC_0_CLOCK_BITS DT_ST_STM32_RTC_40002800_CLOCK_BITS #define DT_RTC_0_CLOCK_BUS DT_ST_STM32_RTC_40002800_CLOCK_BUS + +#define DT_ADC_1_BASE_ADDRESS DT_ST_STM32_ADC_50000000_BASE_ADDRESS +#define DT_ADC_1_IRQ DT_ST_STM32_ADC_50000000_IRQ_0 +#define DT_ADC_1_IRQ_PRI DT_ST_STM32_ADC_50000000_IRQ_0_PRIORITY +#define DT_ADC_1_NAME DT_ST_STM32_ADC_50000000_LABEL +#define DT_ADC_1_CLOCK_BITS DT_ST_STM32_ADC_50000000_CLOCK_BITS_0 +#define DT_ADC_1_CLOCK_BUS DT_ST_STM32_ADC_50000000_CLOCK_BUS_0 + /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/st_stm32/stm32f4/dts_fixup.h b/soc/arm/st_stm32/stm32f4/dts_fixup.h index 4a3c55b4d02..606745d8c94 100644 --- a/soc/arm/st_stm32/stm32f4/dts_fixup.h +++ b/soc/arm/st_stm32/stm32f4/dts_fixup.h @@ -395,4 +395,12 @@ #define DT_RTC_0_CLOCK_BUS DT_ST_STM32_RTC_40002800_CLOCK_BUS #define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL + +#define DT_ADC_1_BASE_ADDRESS DT_ST_STM32_ADC_40012000_BASE_ADDRESS +#define DT_ADC_1_IRQ DT_ST_STM32_ADC_40012000_IRQ_0 +#define DT_ADC_1_IRQ_PRI DT_ST_STM32_ADC_40012000_IRQ_0_PRIORITY +#define DT_ADC_1_NAME DT_ST_STM32_ADC_40012000_LABEL +#define DT_ADC_1_CLOCK_BITS DT_ST_STM32_ADC_40012000_CLOCK_BITS_0 +#define DT_ADC_1_CLOCK_BUS DT_ST_STM32_ADC_40012000_CLOCK_BUS_0 + /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/st_stm32/stm32f7/dts_fixup.h b/soc/arm/st_stm32/stm32f7/dts_fixup.h index 68d6cb32864..5b423b736da 100644 --- a/soc/arm/st_stm32/stm32f7/dts_fixup.h +++ b/soc/arm/st_stm32/stm32f7/dts_fixup.h @@ -386,4 +386,12 @@ #define DT_CAN_1_CLOCK_BITS DT_ST_STM32_CAN_40006400_CLOCK_BITS #define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL + +#define DT_ADC_1_BASE_ADDRESS DT_ST_STM32_ADC_40012000_BASE_ADDRESS +#define DT_ADC_1_IRQ DT_ST_STM32_ADC_40012000_IRQ_0 +#define DT_ADC_1_IRQ_PRI DT_ST_STM32_ADC_40012000_IRQ_0_PRIORITY +#define DT_ADC_1_NAME DT_ST_STM32_ADC_40012000_LABEL +#define DT_ADC_1_CLOCK_BITS DT_ST_STM32_ADC_40012000_CLOCK_BITS_0 +#define DT_ADC_1_CLOCK_BUS DT_ST_STM32_ADC_40012000_CLOCK_BUS_0 + /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/st_stm32/stm32l0/dts_fixup.h b/soc/arm/st_stm32/stm32l0/dts_fixup.h index fd2f5bfff4c..9f2477aa19f 100644 --- a/soc/arm/st_stm32/stm32l0/dts_fixup.h +++ b/soc/arm/st_stm32/stm32l0/dts_fixup.h @@ -132,4 +132,12 @@ #define DT_USB_RAM_SIZE DT_ST_STM32_USB_40005C00_RAM_SIZE #define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL + +#define DT_ADC_1_BASE_ADDRESS DT_ST_STM32_ADC_40012400_BASE_ADDRESS +#define DT_ADC_1_IRQ DT_ST_STM32_ADC_40012400_IRQ_0 +#define DT_ADC_1_IRQ_PRI DT_ST_STM32_ADC_40012400_IRQ_0_PRIORITY +#define DT_ADC_1_NAME DT_ST_STM32_ADC_40012400_LABEL +#define DT_ADC_1_CLOCK_BITS DT_ST_STM32_ADC_40012400_CLOCK_BITS_0 +#define DT_ADC_1_CLOCK_BUS DT_ST_STM32_ADC_40012400_CLOCK_BUS_0 + /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/st_stm32/stm32l4/dts_fixup.h b/soc/arm/st_stm32/stm32l4/dts_fixup.h index f9e12418c4d..25e91075296 100644 --- a/soc/arm/st_stm32/stm32l4/dts_fixup.h +++ b/soc/arm/st_stm32/stm32l4/dts_fixup.h @@ -310,4 +310,12 @@ #define DT_CAN_1_CLOCK_BITS DT_ST_STM32_CAN_40006400_CLOCK_BITS #define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL + +#define DT_ADC_1_BASE_ADDRESS DT_ST_STM32_ADC_50040000_BASE_ADDRESS +#define DT_ADC_1_IRQ DT_ST_STM32_ADC_50040000_IRQ_0 +#define DT_ADC_1_IRQ_PRI DT_ST_STM32_ADC_50040000_IRQ_0_PRIORITY +#define DT_ADC_1_NAME DT_ST_STM32_ADC_50040000_LABEL +#define DT_ADC_1_CLOCK_BITS DT_ST_STM32_ADC_50040000_CLOCK_BITS_0 +#define DT_ADC_1_CLOCK_BUS DT_ST_STM32_ADC_50040000_CLOCK_BUS_0 + /* End of SoC Level DTS fixup file */