From da26dbd08a75c01782c30dc2122a258549dbd822 Mon Sep 17 00:00:00 2001
From: Phuc Pham <phuc.pham.xr@bp.renesas.com>
Date: Mon, 26 May 2025 17:40:29 +0700
Subject: [PATCH] drivers: pinctrl: Add support for Renesas RZ/G2UL

Add pinctrl support for Renesas RZ/G2UL

Signed-off-by: Phuc Pham <phuc.pham.xr@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
---
 .../rzg2ul_smarc/rzg2ul_smarc-pinctrl.dtsi       | 16 ++++++++++++++++
 dts/arm/renesas/rz/rzg/r9a07g043.dtsi            |  6 ++++++
 dts/bindings/pinctrl/renesas,rzg-pinctrl.yaml    |  2 +-
 3 files changed, 23 insertions(+), 1 deletion(-)
 create mode 100644 boards/renesas/rzg2ul_smarc/rzg2ul_smarc-pinctrl.dtsi

diff --git a/boards/renesas/rzg2ul_smarc/rzg2ul_smarc-pinctrl.dtsi b/boards/renesas/rzg2ul_smarc/rzg2ul_smarc-pinctrl.dtsi
new file mode 100644
index 00000000000..13eecfb3d0b
--- /dev/null
+++ b/boards/renesas/rzg2ul_smarc/rzg2ul_smarc-pinctrl.dtsi
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg2-common.h>
+
+&pinctrl {
+	/omit-if-no-ref/ scif0_pins: scif0 {
+		scif0-pinmux {
+			pinmux = <RZG_PINMUX(PORT_06, 3, 6)>, /* RXD */
+				 <RZG_PINMUX(PORT_06, 4, 6)>; /* TXD */
+		};
+	};
+};
diff --git a/dts/arm/renesas/rz/rzg/r9a07g043.dtsi b/dts/arm/renesas/rz/rzg/r9a07g043.dtsi
index 34581b6a7a0..c69572274d9 100644
--- a/dts/arm/renesas/rz/rzg/r9a07g043.dtsi
+++ b/dts/arm/renesas/rz/rzg/r9a07g043.dtsi
@@ -32,6 +32,12 @@
 	};
 
 	soc {
+		pinctrl: pin-controller@41030000 {
+			compatible = "renesas,rzg-pinctrl";
+			reg = <0x41030000 DT_SIZE_K(64)>;
+			reg-names = "pinctrl";
+		};
+
 		scif0: serial@4004b800 {
 			compatible = "renesas,rz-scif-uart";
 			channel = <0>;
diff --git a/dts/bindings/pinctrl/renesas,rzg-pinctrl.yaml b/dts/bindings/pinctrl/renesas,rzg-pinctrl.yaml
index 10aca130db4..17c0e5ac921 100644
--- a/dts/bindings/pinctrl/renesas,rzg-pinctrl.yaml
+++ b/dts/bindings/pinctrl/renesas,rzg-pinctrl.yaml
@@ -10,7 +10,7 @@ description: |
 
     The pre-defined combinations for the RZ/G variants are defined in the below headers
     - pinctrl-rzg-common.h for RZ/G3S
-    - pinctrl-rzg2-common.h for RZ/G2L, RZ/G2LC
+    - pinctrl-rzg2-common.h for RZ/G2L, RZ/G2LC, RZ/G2UL
 
     #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg(2)-common.h>
     example_pins: device_pin {