drivers: pinctrl: Add support for RZ/N2L

This is the initial commit to support pinctrl driver for Renesas RZ/N2L

Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>

boards/renesas/rzn2l_rsk/rzn2l_rsk-pinctrl.dtsi

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzn-common.h>
+
+&pinctrl {
+	/omit-if-no-ref/ sci0_default: sci0_default {
+		sci0-pinmux {
+			pinmux = <RZN_PINMUX(PORT_16, 5, 1)>, /* TXD */
+				 <RZN_PINMUX(PORT_16, 6, 2)>; /* RXD */
+		};
+	};
+
+	/omit-if-no-ref/ sci3_default: sci3_default {
+		sci3-pinmux {
+			pinmux = <RZN_PINMUX(PORT_18, 0, 4)>, /* TXD */
+				 <RZN_PINMUX(PORT_17, 7, 4)>; /* RXD */
+		};
+	};
+
+	/omit-if-no-ref/ irq7_default: irq7_default {
+		irq7-pinmux {
+			pinmux = <RZN_PINMUX(PORT_16, 3, 0)>;
+			input-enable;
+		};
+	};
+};

drivers/pinctrl/renesas/rz/Kconfig

@@ -12,7 +12,7 @@ config PINCTRL_RZT2M
 config PINCTRL_RENESAS_RZ
 	bool "Renesas RZ pin controller driver"
 	default y
-	depends on DT_HAS_RENESAS_RZG_PINCTRL_ENABLED
+	depends on DT_HAS_RENESAS_RZG_PINCTRL_ENABLED || DT_HAS_RENESAS_RZN_PINCTRL_ENABLED
 	select USE_RZ_FSP_IOPORT
 	help
 	  Enable Renesas RZ pinctrl driver.

dts/arm/renesas/rz/rzn/r9a07g084.dtsi

@@ -87,5 +87,10 @@
 				};
 			};
 		};
+
+		pinctrl: pinctrl@800a0000 {
+			compatible = "renesas,rzn-pinctrl";
+			reg = <0x800a0000 0x1000 0x81030c00 0x1000>;
+		};
 	};
 };

dts/bindings/pinctrl/renesas,rzn-pinctrl.yaml

@@ -0,0 +1,95 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+
+description: |
+    The Renesas RZ/N2L pin controller is a node responsible for controlling
+    pin function selection and pin properties, such as routing the TX and RX of UART0
+    to pin 5 and pin 6 of port 16.
+
+    The node has the 'pinctrl' node label set in your SoC's devicetree,
+    so you can modify it like this:
+
+      &pinctrl {
+              /* your modifications go here */
+      };
+
+    All device pin configurations should be placed in child nodes of the
+    'pinctrl' node, as shown in this example:
+
+      /* You can put this in places like a board-pinctrl.dtsi file in
+       * your board directory, or a devicetree overlay in your application.
+       */
+
+      /* include pre-defined combinations for the SoC variant used by the board */
+      #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzn-common.h>
+
+      &pinctrl {
+        uart0_pins: uart0 {
+          group1 {
+            pinmux = <RZN_PINMUX(PORT_16, 5, 1)>; /* TXD */
+          };
+          group2 {
+            pinmux = <RZN_PINMUX(PORT_16, 6, 2)>; /* RXD */
+            input-enable;
+          };
+        };
+      };
+
+    The 'uart0_pins' child node encodes the pin configurations for a
+    particular state of a device; in this case, the default (that is, active)
+    state.
+
+    As shown, pin configurations are organized in groups within each child node.
+    Each group can specify a list of pin function selections in the 'pinmux'
+    property.
+
+    A group can also specify shared pin properties common to all the specified
+    pins, such as the 'input-enable' property in group 2.
+
+compatible: "renesas,rzn-pinctrl"
+
+include: base.yaml
+
+child-binding:
+  description: |
+    Definitions for a pinctrl state.
+  child-binding:
+
+    include:
+      - name: pincfg-node.yaml
+        property-allowlist:
+          - input-enable
+          - output-enable
+          - output-high
+          - bias-pull-up
+          - bias-pull-down
+          - input-schmitt-enable
+
+    properties:
+      pinmux:
+        required: true
+        type: array
+        description: |
+          An array of pins sharing the same group properties. Each
+          element of the array is an integer constructed from the
+          pin number and the alternative function of the pin.
+      drive-strength:
+        type: string
+        enum:
+          - "low"
+          - "middle"
+          - "high"
+          - "ultrahigh"
+        default: "low"
+        description: |
+          The drive strength of a pin, relative to full-driver strength.
+          The default value is "low", which is the reset value.
+      slew-rate:
+        type: string
+        enum:
+          - "slow"
+          - "fast"
+        default: "slow"
+        description: |
+          Select slew rate for a pin. The default is slow, which is the reset value.

include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzn-common.h

@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZN_COMMON_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZN_COMMON_H_
+
+/* Superset list of all possible IO ports. */
+#define PORT_00 0x0000 /* IO port 0 */
+#define PORT_01 0x0100 /* IO port 1 */
+#define PORT_02 0x0200 /* IO port 2 */
+#define PORT_03 0x0300 /* IO port 3 */
+#define PORT_04 0x0400 /* IO port 4 */
+#define PORT_05 0x0500 /* IO port 5 */
+#define PORT_06 0x0600 /* IO port 6 */
+#define PORT_07 0x0700 /* IO port 7 */
+#define PORT_08 0x0800 /* IO port 8 */
+#define PORT_09 0x0900 /* IO port 9 */
+#define PORT_10 0x0A00 /* IO port 10 */
+#define PORT_11 0x0B00 /* IO port 11 */
+#define PORT_12 0x0C00 /* IO port 12 */
+#define PORT_13 0x0D00 /* IO port 13 */
+#define PORT_14 0x0E00 /* IO port 14 */
+#define PORT_15 0x0F00 /* IO port 15 */
+#define PORT_16 0x1000 /* IO port 16 */
+#define PORT_17 0x1100 /* IO port 17 */
+#define PORT_18 0x1200 /* IO port 18 */
+#define PORT_19 0x1300 /* IO port 19 */
+#define PORT_20 0x1400 /* IO port 20 */
+#define PORT_21 0x1500 /* IO port 21 */
+#define PORT_22 0x1600 /* IO port 22 */
+#define PORT_23 0x1700 /* IO port 23 */
+#define PORT_24 0x1800 /* IO port 24 */
+
+/*
+ * Create the value contain port/pin/function information
+ *
+ * port: port number BSP_IO_PORT_00..BSP_IO_PORT_34
+ * pin: pin number
+ * func: pin function
+ */
+#define RZN_PINMUX(port, pin, func) (port | pin | (func << 4))
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZN_COMMON_H_ */

soc/renesas/rz/common/pinctrl_rzn.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZN_H_
+#define ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZN_H_
+
+#include <zephyr/types.h>
+#include <zephyr/devicetree.h>
+#include "r_ioport.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RZN_GET_PORT_PIN(pinmux) (pinmux & ~(0xF << 4))
+#define RZN_GET_FUNC(pinmux)     ((pinmux & 0xF0) >> 4)
+
+/* Porting */
+typedef struct pinctrl_cfg_data_t {
+	uint32_t p_reg: 1;
+	uint32_t pm_reg: 2;
+	uint32_t pmc_reg: 1;
+	uint32_t pfc_reg: 4;
+	uint32_t drct_reg: 6;
+	uint32_t rsel_reg: 1;
+	uint32_t reserved: 17;
+} pinctrl_cfg_data_t;
+
+typedef struct pinctrl_soc_pin_t {
+	bsp_io_port_pin_t port_pin;
+	pinctrl_cfg_data_t config;
+} pinctrl_soc_pin_t;
+
+#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx)                                               \
+	{                                                                                          \
+		.port_pin = RZN_GET_PORT_PIN(DT_PROP_BY_IDX(node_id, prop, idx)),                  \
+		.config =                                                                          \
+			{                                                                          \
+				.p_reg = DT_PROP(node_id, output_high),                            \
+				.pm_reg = DT_PROP(node_id, input_enable) == 1                      \
+						  ? 1U                                             \
+						  : (DT_PROP(node_id, output_enable) == 1 ? 2U     \
+											  : 0U),   \
+				.pmc_reg = 1,                                                      \
+				.pfc_reg = RZN_GET_FUNC(DT_PROP_BY_IDX(node_id, prop, idx)),       \
+				.drct_reg =                                                        \
+					(DT_ENUM_IDX(node_id, drive_strength)) |                   \
+					((DT_PROP(node_id, bias_pull_up) == 1                      \
+						  ? 1U                                             \
+						  : (DT_PROP(node_id, bias_pull_down) == 1 ? 2U    \
+											   : 0))   \
+					 << 2) |                                                   \
+					(DT_PROP(node_id, input_schmitt_enable) << 4) |            \
+					(DT_ENUM_IDX(node_id, slew_rate) << 5),                    \
+				.rsel_reg = 1,                                                     \
+				.reserved = 0,                                                     \
+			},                                                                         \
+	},
+#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop)                                                   \
+	{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux,           \
+				Z_PINCTRL_STATE_PIN_INIT)}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZN_H_ */

soc/renesas/rz/rzn2l/pinctrl_soc.h

@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RZ_RZN2L_PINCTRL_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RZ_RZN2L_PINCTRL_SOC_H_
+
+#include <pinctrl_rzn.h>
+
+#endif /* ZEPHYR_SOC_RENESAS_RZ_RZN2L_PINCTRL_SOC_H_ */