From d9e2171aa9b98cad5cba0aee8dcf2a4cae6cea53 Mon Sep 17 00:00:00 2001 From: Piotr Mienkowski Date: Tue, 7 Aug 2018 14:11:45 +0200 Subject: [PATCH] drivers: flash_gecko: Add flash driver for SiLabs Gecko SoCs Tested with SLWSTK6061A / BRD4250B wireless starter kit. Signed-off-by: Piotr Mienkowski --- .../doc/efm32hg_slstk3400a.rst | 2 + .../efm32wg_stk3800/doc/efm32wg_stk3800.rst | 2 + .../doc/efr32_slwstk6061a.rst | 2 + .../efr32mg_sltb004a/doc/efr32mg_sltb004a.rst | 2 + drivers/flash/CMakeLists.txt | 1 + drivers/flash/Kconfig | 2 + drivers/flash/Kconfig.gecko | 16 ++ drivers/flash/flash_gecko.c | 194 ++++++++++++++++++ dts/arm/silabs/efm32hg.dtsi | 21 +- dts/arm/silabs/efm32hg322f64.dtsi | 12 +- dts/arm/silabs/efm32wg.dtsi | 21 +- dts/arm/silabs/efm32wg990f256.dtsi | 12 +- dts/arm/silabs/efr32fg1p.dtsi | 21 +- dts/arm/silabs/efr32fg1p133f256gm48.dtsi | 12 +- dts/arm/silabs/efr32mg.dtsi | 21 +- dts/arm/silabs/efr32mg12p332f1024gl125.dtsi | 12 +- .../silabs,gecko-flash-controller.yaml | 20 ++ ext/hal/silabs/gecko/CMakeLists.txt | 1 + .../efm32hg/Kconfig.defconfig.efm32hg | 7 + soc/arm/silabs_exx32/efm32hg/dts_fixup.h | 3 + .../efm32wg/Kconfig.defconfig.efm32wg | 7 + soc/arm/silabs_exx32/efm32wg/dts_fixup.h | 3 + .../efr32fg1p/Kconfig.defconfig.efr32fg1p | 7 + soc/arm/silabs_exx32/efr32fg1p/dts_fixup.h | 3 + .../efr32mg12p/Kconfig.defconfig.efr32mg12p | 7 + soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h | 3 + 26 files changed, 378 insertions(+), 36 deletions(-) create mode 100644 drivers/flash/Kconfig.gecko create mode 100644 drivers/flash/flash_gecko.c create mode 100644 dts/bindings/flash_controller/silabs,gecko-flash-controller.yaml diff --git a/boards/arm/efm32hg_slstk3400a/doc/efm32hg_slstk3400a.rst b/boards/arm/efm32hg_slstk3400a/doc/efm32hg_slstk3400a.rst index 90ca3f1c88a..92b55ad448a 100644 --- a/boards/arm/efm32hg_slstk3400a/doc/efm32hg_slstk3400a.rst +++ b/boards/arm/efm32hg_slstk3400a/doc/efm32hg_slstk3400a.rst @@ -52,6 +52,8 @@ The efm32hg_slstk3400 board configuration supports the following hardware featur +-----------+------------+-------------------------------------+ | SYSTICK | on-chip | systick | +-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ | GPIO | on-chip | gpio | +-----------+------------+-------------------------------------+ | USART | on-chip | serial port-polling; | diff --git a/boards/arm/efm32wg_stk3800/doc/efm32wg_stk3800.rst b/boards/arm/efm32wg_stk3800/doc/efm32wg_stk3800.rst index aeceefcc962..24b2b3b2b68 100644 --- a/boards/arm/efm32wg_stk3800/doc/efm32wg_stk3800.rst +++ b/boards/arm/efm32wg_stk3800/doc/efm32wg_stk3800.rst @@ -50,6 +50,8 @@ The efm32wg_stk3800oard configuration supports the following hardware features: +-----------+------------+-------------------------------------+ | SYSTICK | on-chip | systick | +-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ | GPIO | on-chip | gpio | +-----------+------------+-------------------------------------+ | UART | on-chip | serial port-polling; | diff --git a/boards/arm/efr32_slwstk6061a/doc/efr32_slwstk6061a.rst b/boards/arm/efr32_slwstk6061a/doc/efr32_slwstk6061a.rst index c4e746ab00b..0ea0625fbbf 100644 --- a/boards/arm/efr32_slwstk6061a/doc/efr32_slwstk6061a.rst +++ b/boards/arm/efr32_slwstk6061a/doc/efr32_slwstk6061a.rst @@ -60,6 +60,8 @@ The efr32_slwstk6061a board configuration supports the following hardware featur +-----------+------------+-------------------------------------+ | SYSTICK | on-chip | systick | +-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ | GPIO | on-chip | gpio | +-----------+------------+-------------------------------------+ | UART | on-chip | serial port-polling; | diff --git a/boards/arm/efr32mg_sltb004a/doc/efr32mg_sltb004a.rst b/boards/arm/efr32mg_sltb004a/doc/efr32mg_sltb004a.rst index 0f41a01d041..97efcd61f60 100644 --- a/boards/arm/efr32mg_sltb004a/doc/efr32mg_sltb004a.rst +++ b/boards/arm/efr32mg_sltb004a/doc/efr32mg_sltb004a.rst @@ -63,6 +63,8 @@ The efr32mg_sltb004a board configuration supports the following hardware feature +-----------+------------+-------------------------------------+ | SYSTICK | on-chip | systick | +-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ | GPIO | on-chip | gpio | +-----------+------------+-------------------------------------+ | UART | on-chip | serial port-polling; | diff --git a/drivers/flash/CMakeLists.txt b/drivers/flash/CMakeLists.txt index 66de50c9419..0716831d227 100644 --- a/drivers/flash/CMakeLists.txt +++ b/drivers/flash/CMakeLists.txt @@ -8,6 +8,7 @@ zephyr_library_sources_ifdef(CONFIG_FLASH_PAGE_LAYOUT flash_page_layout.c) zephyr_library_sources_ifdef(CONFIG_USERSPACE flash_handlers.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_SAM0 flash_sam0.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_NIOS2_QSPI soc_flash_nios2_qspi.c) +zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_GECKO flash_gecko.c) if(CONFIG_SOC_SERIES_STM32F0X) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_STM32 diff --git a/drivers/flash/Kconfig b/drivers/flash/Kconfig index 61ba2ef59f7..7d786182a71 100644 --- a/drivers/flash/Kconfig +++ b/drivers/flash/Kconfig @@ -85,6 +85,8 @@ config SOC_FLASH_NIOS2_QSPI_DEV_NAME help Specify the device name for the QSPI flash driver. +source "drivers/flash/Kconfig.gecko" + source "drivers/flash/Kconfig.qmsi" source "drivers/flash/Kconfig.stm32" diff --git a/drivers/flash/Kconfig.gecko b/drivers/flash/Kconfig.gecko new file mode 100644 index 00000000000..626bbe1271b --- /dev/null +++ b/drivers/flash/Kconfig.gecko @@ -0,0 +1,16 @@ +# Kconfig - Silicon Labs Gecko flash driver config +# +# Copyright (c) 2018, Piotr Mienkowski +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FLASH_GECKO + bool "Silicon Labs Gecko flash driver" + depends on FLASH && SOC_FAMILY_EXX32 + select FLASH_HAS_DRIVER_ENABLED + help + Enable Silicon Labs Gecko series internal flash driver. + +if SOC_FLASH_GECKO + +endif # SOC_FLASH_GECKO diff --git a/drivers/flash/flash_gecko.c b/drivers/flash/flash_gecko.c new file mode 100644 index 00000000000..a6a16e12fd4 --- /dev/null +++ b/drivers/flash/flash_gecko.c @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2018, Piotr Mienkowski + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL +#include +LOG_MODULE_REGISTER(flash_gecko); + +struct flash_gecko_data { + struct k_sem mutex; +}; + +#define DEV_NAME(dev) ((dev)->config->name) +#define DEV_DATA(dev) \ + ((struct flash_gecko_data *const)(dev)->driver_data) + +static bool write_range_is_valid(off_t offset, u32_t size); +static bool read_range_is_valid(off_t offset, u32_t size); +static int erase_flash_block(off_t offset, size_t size); + +static int flash_gecko_read(struct device *dev, off_t offset, void *data, + size_t size) +{ + if (!read_range_is_valid(offset, size)) { + return -EINVAL; + } + + if (!size) { + return 0; + } + + memcpy(data, (u8_t *)CONFIG_FLASH_BASE_ADDRESS + offset, size); + + return 0; +} + +static int flash_gecko_write(struct device *dev, off_t offset, + const void *data, size_t size) +{ + struct flash_gecko_data *const dev_data = DEV_DATA(dev); + MSC_Status_TypeDef msc_ret; + void *address; + int ret = 0; + + if (!write_range_is_valid(offset, size)) { + return -EINVAL; + } + + if (!size) { + return 0; + } + + k_sem_take(&dev_data->mutex, K_FOREVER); + + address = (u8_t *)CONFIG_FLASH_BASE_ADDRESS + offset; + msc_ret = MSC_WriteWord(address, data, size); + if (msc_ret < 0) { + ret = -EIO; + } + + k_sem_give(&dev_data->mutex); + + return ret; +} + +static int flash_gecko_erase(struct device *dev, off_t offset, size_t size) +{ + struct flash_gecko_data *const dev_data = DEV_DATA(dev); + int ret; + + if (!read_range_is_valid(offset, size)) { + return -EINVAL; + } + + if ((offset % FLASH_PAGE_SIZE) != 0) { + LOG_ERR("offset %x: not on a page boundary", offset); + return -EINVAL; + } + + if ((size % FLASH_PAGE_SIZE) != 0) { + LOG_ERR("size %x: not multiple of a page size", size); + return -EINVAL; + } + + if (!size) { + return 0; + } + + k_sem_take(&dev_data->mutex, K_FOREVER); + + ret = erase_flash_block(offset, size); + + k_sem_give(&dev_data->mutex); + + return ret; +} + +static int flash_gecko_write_protection(struct device *dev, bool enable) +{ + struct flash_gecko_data *const dev_data = DEV_DATA(dev); + int ret = 0; + + k_sem_take(&dev_data->mutex, K_FOREVER); + + if (enable) { + /* Lock the MSC module. */ + MSC->LOCK = 0; + } else { + /* Unlock the MSC module. */ + MSC->LOCK = MSC_UNLOCK_CODE; + } + + k_sem_give(&dev_data->mutex); + + return ret; +} + +/* Note: + * - A flash address to write to must be aligned to words. + * - Number of bytes to write must be divisible by 4. + */ +static bool write_range_is_valid(off_t offset, u32_t size) +{ + return read_range_is_valid(offset, size) + && (offset % sizeof(u32_t) == 0) + && (size % 4 == 0); +} + +static bool read_range_is_valid(off_t offset, u32_t size) +{ + return (offset + size) <= (CONFIG_FLASH_SIZE * 1024); +} + +static int erase_flash_block(off_t offset, size_t size) +{ + MSC_Status_TypeDef msc_ret; + void *address; + int ret = 0; + + for (off_t tmp = offset; tmp < offset + size; tmp += FLASH_PAGE_SIZE) { + address = (u8_t *)CONFIG_FLASH_BASE_ADDRESS + tmp; + msc_ret = MSC_ErasePage(address); + if (msc_ret < 0) { + ret = -EIO; + break; + } + } + + return ret; +} + +static int flash_gecko_init(struct device *dev) +{ + struct flash_gecko_data *const dev_data = DEV_DATA(dev); + + k_sem_init(&dev_data->mutex, 1, 1); + + MSC_Init(); + + /* Lock the MSC module. */ + MSC->LOCK = 0; + + LOG_INF("Device %s initialized", DEV_NAME(dev)); + + return 0; +} + +static const struct flash_driver_api flash_gecko_driver_api = { + .read = flash_gecko_read, + .write = flash_gecko_write, + .erase = flash_gecko_erase, + .write_protection = flash_gecko_write_protection, + /* FLASH_WRITE_BLOCK_SIZE is extracted from device tree as flash node + * property 'write-block-size'. + */ + .write_block_size = FLASH_WRITE_BLOCK_SIZE, +}; + +static struct flash_gecko_data flash_gecko_0_data; + +DEVICE_AND_API_INIT(flash_gecko_0, FLASH_DEV_NAME, + flash_gecko_init, &flash_gecko_0_data, NULL, POST_KERNEL, + CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &flash_gecko_driver_api); diff --git a/dts/arm/silabs/efm32hg.dtsi b/dts/arm/silabs/efm32hg.dtsi index 9ce8e59db82..d6946db5feb 100644 --- a/dts/arm/silabs/efm32hg.dtsi +++ b/dts/arm/silabs/efm32hg.dtsi @@ -12,17 +12,28 @@ }; }; - flash0: flash@0 { - compatible = "soc-nv-flash"; - label = "FLASH_0"; - }; - sram0: memory@20000000 { device_type = "memory"; compatible = "mmio-sram"; }; soc { + flash-controller@400c0000 { + compatible = "silabs,gecko-flash-controller"; + label = "FLASH_CTRL"; + reg = <0x400c0000 0x5c>; + interrupts = <15 0>; + + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@0 { + compatible = "soc-nv-flash"; + label = "FLASH_0"; + write-block-size = <4>; + }; + }; + usart0: usart@4000c000 { /* USART0 */ compatible = "silabs,gecko-usart"; reg = <0x4000c000 0x400>; diff --git a/dts/arm/silabs/efm32hg322f64.dtsi b/dts/arm/silabs/efm32hg322f64.dtsi index 974eee4ebd1..a47bb9265b0 100644 --- a/dts/arm/silabs/efm32hg322f64.dtsi +++ b/dts/arm/silabs/efm32hg322f64.dtsi @@ -8,11 +8,15 @@ #include / { - flash0: flash@0 { - reg = <0 DT_SIZE_K(64)>; - }; - sram0: memory@20000000 { reg = <0x20000000 DT_SIZE_K(8)>; }; + + soc { + flash-controller@400c0000 { + flash0: flash@0 { + reg = <0 DT_SIZE_K(64)>; + }; + }; + }; }; diff --git a/dts/arm/silabs/efm32wg.dtsi b/dts/arm/silabs/efm32wg.dtsi index 4d20f98ac9d..13425fb9b25 100644 --- a/dts/arm/silabs/efm32wg.dtsi +++ b/dts/arm/silabs/efm32wg.dtsi @@ -12,17 +12,28 @@ }; }; - flash0: flash@0 { - compatible = "soc-nv-flash"; - label = "FLASH_0"; - }; - sram0: memory@20000000 { device_type = "memory"; compatible = "mmio-sram"; }; soc { + flash-controller@400c0000 { + compatible = "silabs,gecko-flash-controller"; + label = "FLASH_CTRL"; + reg = <0x400c0000 0x78>; + interrupts = <35 0>; + + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@0 { + compatible = "soc-nv-flash"; + label = "FLASH_0"; + write-block-size = <4>; + }; + }; + usart0: usart@4000c000 { /* USART0 */ compatible = "silabs,gecko-usart"; reg = <0x4000c000 0x400>; diff --git a/dts/arm/silabs/efm32wg990f256.dtsi b/dts/arm/silabs/efm32wg990f256.dtsi index 42f83a32779..bb9d6426fec 100644 --- a/dts/arm/silabs/efm32wg990f256.dtsi +++ b/dts/arm/silabs/efm32wg990f256.dtsi @@ -8,11 +8,15 @@ #include / { - flash@0 { - reg = <0 DT_SIZE_K(256)>; - }; - sram0: memory@20000000 { reg = <0x20000000 DT_SIZE_K(32)>; }; + + soc { + flash-controller@400c0000 { + flash0: flash@0 { + reg = <0 DT_SIZE_K(256)>; + }; + }; + }; }; diff --git a/dts/arm/silabs/efr32fg1p.dtsi b/dts/arm/silabs/efr32fg1p.dtsi index fc121727098..4544df0ae22 100644 --- a/dts/arm/silabs/efr32fg1p.dtsi +++ b/dts/arm/silabs/efr32fg1p.dtsi @@ -12,17 +12,28 @@ }; }; - flash0: flash@0 { - compatible = "soc-nv-flash"; - label = "FLASH_0"; - }; - sram0: memory@20000000 { device_type = "memory"; compatible = "mmio-sram"; }; soc { + flash-controller@400e0000 { + compatible = "silabs,gecko-flash-controller"; + label = "FLASH_CTRL"; + reg = <0x400e0000 0x78>; + interrupts = <24 0>; + + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@0 { + compatible = "soc-nv-flash"; + label = "FLASH_0"; + write-block-size = <4>; + }; + }; + usart0: usart@40010000 { /* USART0 */ compatible = "silabs,gecko-usart"; reg = <0x40010000 0x400>; diff --git a/dts/arm/silabs/efr32fg1p133f256gm48.dtsi b/dts/arm/silabs/efr32fg1p133f256gm48.dtsi index b22d00552db..6325896638b 100644 --- a/dts/arm/silabs/efr32fg1p133f256gm48.dtsi +++ b/dts/arm/silabs/efr32fg1p133f256gm48.dtsi @@ -8,11 +8,15 @@ #include / { - flash@0 { - reg = <0 DT_SIZE_K(256)>; - }; - sram0: memory@20000000 { reg = <0x20000000 DT_SIZE_K(32)>; }; + + soc { + flash-controller@400e0000 { + flash0: flash@0 { + reg = <0 DT_SIZE_K(256)>; + }; + }; + }; }; diff --git a/dts/arm/silabs/efr32mg.dtsi b/dts/arm/silabs/efr32mg.dtsi index f45c8b56856..f3ca7994eec 100644 --- a/dts/arm/silabs/efr32mg.dtsi +++ b/dts/arm/silabs/efr32mg.dtsi @@ -13,17 +13,28 @@ }; }; - flash0: flash@0 { - compatible = "soc-nv-flash"; - label = "FLASH_0"; - }; - sram0: memory@20000000 { device_type = "memory"; compatible = "mmio-sram"; }; soc { + flash-controller@400e0000 { + compatible = "silabs,gecko-flash-controller"; + label = "FLASH_CTRL"; + reg = <0x400e0000 0x104>; + interrupts = <25 0>; + + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@0 { + compatible = "soc-nv-flash"; + label = "FLASH_0"; + write-block-size = <4>; + }; + }; + usart0: usart@40010000 { /* USART0 */ compatible = "silabs,gecko-usart"; reg = <0x40010000 0x400>; diff --git a/dts/arm/silabs/efr32mg12p332f1024gl125.dtsi b/dts/arm/silabs/efr32mg12p332f1024gl125.dtsi index a9502070145..78830a5c6d2 100644 --- a/dts/arm/silabs/efr32mg12p332f1024gl125.dtsi +++ b/dts/arm/silabs/efr32mg12p332f1024gl125.dtsi @@ -8,11 +8,15 @@ #include / { - flash@0 { - reg = <0 DT_SIZE_K(1024)>; - }; - sram0: memory@20000000 { reg = <0x20000000 DT_SIZE_K(256)>; }; + + soc { + flash-controller@400e0000 { + flash0: flash@0 { + reg = <0 DT_SIZE_K(1024)>; + }; + }; + }; }; diff --git a/dts/bindings/flash_controller/silabs,gecko-flash-controller.yaml b/dts/bindings/flash_controller/silabs,gecko-flash-controller.yaml new file mode 100644 index 00000000000..8e59cc191df --- /dev/null +++ b/dts/bindings/flash_controller/silabs,gecko-flash-controller.yaml @@ -0,0 +1,20 @@ +# +# Copyright (c) 2018, Piotr Mienkowski +# +# SPDX-License-Identifier: Apache-2.0 +# +--- +title: Silicon Labs Gecko Flash Controller +version: 0.1 + +description: > + This binding gives a base representation of the Silicon Labs Gecko Flash Controller + +inherits: + !include flash-controller.yaml + +properties: + compatible: + constraint: "silabs,gecko-flash-controller" + +... diff --git a/ext/hal/silabs/gecko/CMakeLists.txt b/ext/hal/silabs/gecko/CMakeLists.txt index 40b385dacc1..84dea5d9067 100644 --- a/ext/hal/silabs/gecko/CMakeLists.txt +++ b/ext/hal/silabs/gecko/CMakeLists.txt @@ -29,6 +29,7 @@ zephyr_sources_ifdef(CONFIG_GPIO_GECKO emlib/src/em_gpio.c) zephyr_sources_ifdef(CONFIG_UART_GECKO emlib/src/em_usart.c) zephyr_sources_ifdef(CONFIG_LEUART_GECKO emlib/src/em_leuart.c) zephyr_sources_ifdef(CONFIG_I2C_GECKO emlib/src/em_i2c.c) +zephyr_sources_ifdef(CONFIG_SOC_FLASH_GECKO emlib/src/em_msc.c) zephyr_sources_ifdef(CONFIG_SOC_SERIES_EFM32WG Device/SiliconLabs/EFM32WG/Source/system_efm32wg.c) zephyr_sources_ifdef(CONFIG_SOC_SERIES_EFR32FG1P Device/SiliconLabs/EFR32FG1P/Source/system_efr32fg1p.c) zephyr_sources_ifdef(CONFIG_SOC_SERIES_EFM32HG Device/SiliconLabs/EFM32HG/Source/system_efm32hg.c) diff --git a/soc/arm/silabs_exx32/efm32hg/Kconfig.defconfig.efm32hg b/soc/arm/silabs_exx32/efm32hg/Kconfig.defconfig.efm32hg index 8e28faedfc2..d9341dfadcd 100644 --- a/soc/arm/silabs_exx32/efm32hg/Kconfig.defconfig.efm32hg +++ b/soc/arm/silabs_exx32/efm32hg/Kconfig.defconfig.efm32hg @@ -29,4 +29,11 @@ config UART_GECKO endif # SERIAL +if FLASH + +config SOC_FLASH_GECKO + def_bool y + +endif # FLASH + endif # SOC_EFM32HG diff --git a/soc/arm/silabs_exx32/efm32hg/dts_fixup.h b/soc/arm/silabs_exx32/efm32hg/dts_fixup.h index df2446e9436..b51683a579d 100644 --- a/soc/arm/silabs_exx32/efm32hg/dts_fixup.h +++ b/soc/arm/silabs_exx32/efm32hg/dts_fixup.h @@ -8,6 +8,9 @@ #define CONFIG_NUM_IRQ_PRIO_BITS ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define FLASH_DEV_BASE_ADDRESS SILABS_GECKO_FLASH_CONTROLLER_400C0000_BASE_ADDRESS +#define FLASH_DEV_NAME SILABS_GECKO_FLASH_CONTROLLER_400C0000_LABEL + #define CONFIG_USART_GECKO_0_BASE_ADDRESS SILABS_GECKO_USART_4000C000_BASE_ADDRESS #define CONFIG_USART_GECKO_0_CURRENT_SPEED SILABS_GECKO_USART_4000C000_CURRENT_SPEED #define CONFIG_USART_GECKO_0_IRQ_RX SILABS_GECKO_USART_4000C000_IRQ_0 diff --git a/soc/arm/silabs_exx32/efm32wg/Kconfig.defconfig.efm32wg b/soc/arm/silabs_exx32/efm32wg/Kconfig.defconfig.efm32wg index 99cfea2ac21..b5ffa920818 100644 --- a/soc/arm/silabs_exx32/efm32wg/Kconfig.defconfig.efm32wg +++ b/soc/arm/silabs_exx32/efm32wg/Kconfig.defconfig.efm32wg @@ -29,4 +29,11 @@ config UART_GECKO endif # SERIAL +if FLASH + +config SOC_FLASH_GECKO + def_bool y + +endif # FLASH + endif # SOC_EFM32 diff --git a/soc/arm/silabs_exx32/efm32wg/dts_fixup.h b/soc/arm/silabs_exx32/efm32wg/dts_fixup.h index 9ae70e5c9b7..c00c94f9fe3 100644 --- a/soc/arm/silabs_exx32/efm32wg/dts_fixup.h +++ b/soc/arm/silabs_exx32/efm32wg/dts_fixup.h @@ -8,6 +8,9 @@ #define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define FLASH_DEV_BASE_ADDRESS SILABS_GECKO_FLASH_CONTROLLER_400C0000_BASE_ADDRESS +#define FLASH_DEV_NAME SILABS_GECKO_FLASH_CONTROLLER_400C0000_LABEL + #define CONFIG_USART_GECKO_0_BASE_ADDRESS SILABS_GECKO_USART_4000C000_BASE_ADDRESS #define CONFIG_USART_GECKO_0_CURRENT_SPEED SILABS_GECKO_USART_4000C000_CURRENT_SPEED #define CONFIG_USART_GECKO_0_IRQ_RX SILABS_GECKO_USART_4000C000_IRQ_0 diff --git a/soc/arm/silabs_exx32/efr32fg1p/Kconfig.defconfig.efr32fg1p b/soc/arm/silabs_exx32/efr32fg1p/Kconfig.defconfig.efr32fg1p index 28b47eef44e..bed715fceb0 100644 --- a/soc/arm/silabs_exx32/efr32fg1p/Kconfig.defconfig.efr32fg1p +++ b/soc/arm/silabs_exx32/efr32fg1p/Kconfig.defconfig.efr32fg1p @@ -29,4 +29,11 @@ config UART_GECKO endif # SERIAL +if FLASH + +config SOC_FLASH_GECKO + def_bool y + +endif # FLASH + endif # SOC_EFR32FG1P diff --git a/soc/arm/silabs_exx32/efr32fg1p/dts_fixup.h b/soc/arm/silabs_exx32/efr32fg1p/dts_fixup.h index 51799a8e325..d09fa3b218d 100644 --- a/soc/arm/silabs_exx32/efr32fg1p/dts_fixup.h +++ b/soc/arm/silabs_exx32/efr32fg1p/dts_fixup.h @@ -8,6 +8,9 @@ #define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define FLASH_DEV_BASE_ADDRESS SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS +#define FLASH_DEV_NAME SILABS_GECKO_FLASH_CONTROLLER_400E0000_LABEL + #define CONFIG_USART_GECKO_0_BASE_ADDRESS SILABS_GECKO_USART_40010000_BASE_ADDRESS #define CONFIG_USART_GECKO_0_CURRENT_SPEED SILABS_GECKO_USART_40010000_CURRENT_SPEED #define CONFIG_USART_GECKO_0_IRQ_RX SILABS_GECKO_USART_40010000_IRQ_0 diff --git a/soc/arm/silabs_exx32/efr32mg12p/Kconfig.defconfig.efr32mg12p b/soc/arm/silabs_exx32/efr32mg12p/Kconfig.defconfig.efr32mg12p index fd9fc363e6d..c285be338f7 100644 --- a/soc/arm/silabs_exx32/efr32mg12p/Kconfig.defconfig.efr32mg12p +++ b/soc/arm/silabs_exx32/efr32mg12p/Kconfig.defconfig.efr32mg12p @@ -39,4 +39,11 @@ config I2C_GECKO endif # I2C +if FLASH + +config SOC_FLASH_GECKO + def_bool y + +endif # FLASH + endif # SOC_EFR32MG12P diff --git a/soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h b/soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h index fadfc113c88..2cc6d0d63ac 100644 --- a/soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h +++ b/soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h @@ -8,6 +8,9 @@ #define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define FLASH_DEV_BASE_ADDRESS SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS +#define FLASH_DEV_NAME SILABS_GECKO_FLASH_CONTROLLER_400E0000_LABEL + #define CONFIG_USART_GECKO_0_BASE_ADDRESS SILABS_GECKO_USART_40010000_BASE_ADDRESS #define CONFIG_USART_GECKO_0_CURRENT_SPEED SILABS_GECKO_USART_40010000_CURRENT_SPEED #define CONFIG_USART_GECKO_0_IRQ_RX SILABS_GECKO_USART_40010000_IRQ_0