From d9dedff71a3ae3840f677b0c68b98d4fb558e679 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Mon, 9 Jun 2025 22:14:50 +0200 Subject: [PATCH] drivers: gpio: rpi_pico: route ISR to the right irq_ctrl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit gpio_rpi_isr() always addressed io_bank0->proc0_irq_ctrl, so any interrupts taken while code was running on core 1 were invisible and left pending. Use get_core_num() to pick proc1_irq_ctrl when the ISR executes on core 1, ensuring callbacks fire from both cores. Also fix stray `iobank0_hw` symbol for the correct `io_bank0_hw`. Signed-off-by: Benjamin Cabé --- drivers/gpio/gpio_rpi_pico.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/gpio_rpi_pico.c b/drivers/gpio/gpio_rpi_pico.c index 029cda4e6f4..9aee0d577a3 100644 --- a/drivers/gpio/gpio_rpi_pico.c +++ b/drivers/gpio/gpio_rpi_pico.c @@ -392,7 +392,8 @@ static void gpio_rpi_isr(const struct device *dev) uint32_t events; uint32_t pin; - irq_ctrl_base = &iobank0_hw->proc0_irq_ctrl; + irq_ctrl_base = get_core_num() ? &io_bank0_hw->proc1_irq_ctrl + : &io_bank0_hw->proc0_irq_ctrl; for (pin = 0; pin < NUM_BANK0_GPIOS; pin++) { status_reg = &irq_ctrl_base->ints[pin / 8]; events = (*status_reg >> 4 * (pin % 8)) & ALL_EVENTS;