From d9a416f38d5d31af50a12c64ab5ff4a7858489e0 Mon Sep 17 00:00:00 2001 From: Tomasz Leman Date: Fri, 25 Nov 2022 00:28:33 +0100 Subject: [PATCH] power_domain: intel_adsp: code update This patch contains several small changes to the intel adsp power domain. - include missing header, - replacing sys_write32/sys_read32 with sys_write16/sys_read16 since DfPWRCTL is a 16 bit register, - renaming struct to be more representing what it is, - passing register address, not a value to the sys_read/sys_write functions, - pd_intel_adsp_init is now returning actual status. Signed-off-by: Tomasz Leman --- .../power_domain/power_domain_intel_adsp.c | 26 +++++++++---------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/power_domain/power_domain_intel_adsp.c b/drivers/power_domain/power_domain_intel_adsp.c index 38550aaeee2..88caaa7d32a 100644 --- a/drivers/power_domain/power_domain_intel_adsp.c +++ b/drivers/power_domain/power_domain_intel_adsp.c @@ -7,25 +7,26 @@ #include #include #include +#include #include LOG_MODULE_REGISTER(power_domain_intel_adsp, LOG_LEVEL_INF); -struct pg_registers { +struct pg_bits { uint32_t SPA_bit; uint32_t CPA_bit; }; -static int pd_intel_adsp_set_power_enable(struct pg_registers *reg, bool power_enable) +static int pd_intel_adsp_set_power_enable(struct pg_bits *bits, bool power_enable) { - uint32_t SPA_bit_mask = BIT(reg->SPA_bit); + uint16_t SPA_bit_mask = BIT(bits->SPA_bit); if (power_enable) { - sys_write32(sys_read32(ACE_DfPMCCU->dfpwrctl) | SPA_bit_mask, - ACE_DfPMCCU->dfpwrctl); + sys_write16(sys_read16((mem_addr_t)&ACE_DfPMCCU.dfpwrctl) | SPA_bit_mask, + (mem_addr_t)&ACE_DfPMCCU.dfpwrctl); } else { - sys_write32(sys_read32(ACE_DfPMCCU->dfpwrctl) & ~(SPA_bit_mask), - ACE_DfPMCCU->dfpwrctl); + sys_write16(sys_read16((mem_addr_t)&ACE_DfPMCCU.dfpwrctl) & ~(SPA_bit_mask), + (mem_addr_t)&ACE_DfPMCCU.dfpwrctl); } return 0; @@ -33,16 +34,16 @@ static int pd_intel_adsp_set_power_enable(struct pg_registers *reg, bool power_e static int pd_intel_adsp_pm_action(const struct device *dev, enum pm_device_action action) { - struct pg_registers *reg_data = (struct pg_registers *)dev->data; + struct pg_bits *reg_bits = (struct pg_bits *)dev->data; switch (action) { case PM_DEVICE_ACTION_RESUME: pm_device_children_action_run(dev, PM_DEVICE_ACTION_TURN_ON, NULL); - pd_intel_adsp_set_power_enable(reg_data, true); + pd_intel_adsp_set_power_enable(reg_bits, true); break; case PM_DEVICE_ACTION_SUSPEND: pm_device_children_action_run(dev, PM_DEVICE_ACTION_TURN_OFF, NULL); - pd_intel_adsp_set_power_enable(reg_data, false); + pd_intel_adsp_set_power_enable(reg_bits, false); break; case PM_DEVICE_ACTION_TURN_ON: break; @@ -57,14 +58,13 @@ static int pd_intel_adsp_pm_action(const struct device *dev, enum pm_device_acti static int pd_intel_adsp_init(const struct device *dev) { pm_device_init_suspended(dev); - pm_device_runtime_enable(dev); - return 0; + return pm_device_runtime_enable(dev); } #define DT_DRV_COMPAT intel_adsp_power_domain #define POWER_DOMAIN_DEVICE(id) \ - static struct pg_registers pd_pg_reg##id = { \ + static struct pg_bits pd_pg_reg##id = { \ .SPA_bit = DT_INST_PROP(id, bit_position), \ .CPA_bit = DT_INST_PROP(id, bit_position), \ }; \