michaelh/zephyr
1
0
Fork 0
Code Releases Activity

power_domain: intel_adsp: code update

Browse source 
This patch contains several small changes to the intel adsp power
domain.

- include missing header,
- replacing sys_write32/sys_read32 with sys_write16/sys_read16 since
  DfPWRCTL is a 16 bit register,
- renaming struct to be more representing what it is,
- passing register address, not a value to the sys_read/sys_write
  functions,
- pd_intel_adsp_init is now returning actual status.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This commit is contained in:
Tomasz Leman 2022-11-25 00:28:33 +01:00 • committed by Anas Nashif
commit d9a416f38d
1 changed files with 13 additions and 13 deletions
Download patch file Download diff file Expand all files Collapse all files

26
drivers/power_domain/power_domain_intel_adsp.c
View file

@ -7,25 +7,26 @@
#include <zephyr/kernel.h>
#include <zephyr/pm/device.h>
#include <zephyr/pm/device_runtime.h>
#include <adsp_shim.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(power_domain_intel_adsp, LOG_LEVEL_INF);
struct pg_registers {
struct pg_bits {
uint32_t SPA_bit;
uint32_t CPA_bit;
};
static int pd_intel_adsp_set_power_enable(struct pg_registers *reg, bool power_enable)
static int pd_intel_adsp_set_power_enable(struct pg_bits *bits, bool power_enable)
{
uint32_t SPA_bit_mask = BIT(reg->SPA_bit);
uint16_t SPA_bit_mask = BIT(bits->SPA_bit);
if (power_enable) {
sys_write32(sys_read32(ACE_DfPMCCU->dfpwrctl) | SPA_bit_mask,
ACE_DfPMCCU->dfpwrctl);
sys_write16(sys_read16((mem_addr_t)&ACE_DfPMCCU.dfpwrctl) | SPA_bit_mask,
(mem_addr_t)&ACE_DfPMCCU.dfpwrctl);
} else {
sys_write32(sys_read32(ACE_DfPMCCU->dfpwrctl) & ~(SPA_bit_mask),
ACE_DfPMCCU->dfpwrctl);
sys_write16(sys_read16((mem_addr_t)&ACE_DfPMCCU.dfpwrctl) & ~(SPA_bit_mask),
(mem_addr_t)&ACE_DfPMCCU.dfpwrctl);
}
return 0;
@ -33,16 +34,16 @@ static int pd_intel_adsp_set_power_enable(struct pg_registers *reg, bool power_e
static int pd_intel_adsp_pm_action(const struct device *dev, enum pm_device_action action)
{
struct pg_registers *reg_data = (struct pg_registers *)dev->data;
struct pg_bits *reg_bits = (struct pg_bits *)dev->data;
switch (action) {
case PM_DEVICE_ACTION_RESUME:
pm_device_children_action_run(dev, PM_DEVICE_ACTION_TURN_ON, NULL);
pd_intel_adsp_set_power_enable(reg_data, true);
pd_intel_adsp_set_power_enable(reg_bits, true);
break;
case PM_DEVICE_ACTION_SUSPEND:
pm_device_children_action_run(dev, PM_DEVICE_ACTION_TURN_OFF, NULL);
pd_intel_adsp_set_power_enable(reg_data, false);
pd_intel_adsp_set_power_enable(reg_bits, false);
break;
case PM_DEVICE_ACTION_TURN_ON:
break;
@ -57,14 +58,13 @@ static int pd_intel_adsp_pm_action(const struct device *dev, enum pm_device_acti
static int pd_intel_adsp_init(const struct device *dev)
{
pm_device_init_suspended(dev);
pm_device_runtime_enable(dev);
return 0;
return pm_device_runtime_enable(dev);
}
#define DT_DRV_COMPAT intel_adsp_power_domain
#define POWER_DOMAIN_DEVICE(id) \
static struct pg_registers pd_pg_reg##id = { \
static struct pg_bits pd_pg_reg##id = { \
.SPA_bit = DT_INST_PROP(id, bit_position), \
.CPA_bit = DT_INST_PROP(id, bit_position), \
}; \