drivers: spi: Add cypress PSoC-6 scb spi driver
Add Cypress PSoC-6 SCB[spi] driver. Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
This commit is contained in:
Gerson Fernando Budke
Carles Cufí
parent
3155b762a6
commit
d999531f7f
6 changed files with 529 additions and 0 deletions
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@ -23,5 +23,6 @@ zephyr_library_sources_ifdef(CONFIG_SPI_GECKO spi_gecko.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_XLNX_AXI_QUADSPI spi_xlnx_axi_quadspi.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_XLNX_AXI_QUADSPI spi_xlnx_axi_quadspi.c)
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zephyr_library_sources_ifdef(CONFIG_ESP32_SPIM spi_esp32_spim.c)
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zephyr_library_sources_ifdef(CONFIG_ESP32_SPIM spi_esp32_spim.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_TEST spi_test.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_TEST spi_test.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_PSOC6 spi_psoc6.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE spi_handlers.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE spi_handlers.c)
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@ -73,4 +73,6 @@ source "drivers/spi/Kconfig.esp32"
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source "drivers/spi/Kconfig.test"
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source "drivers/spi/Kconfig.test"
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source "drivers/spi/Kconfig.psoc6"
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endif # SPI
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endif # SPI
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10
drivers/spi/Kconfig.psoc6
Normal file
10
drivers/spi/Kconfig.psoc6
Normal file
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@ -0,0 +1,10 @@
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# Cypress SCB[SPI] configuration
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# Copyright (c) 2021 ATL Electronics
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# SPDX-License-Identifier: Apache-2.0
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config SPI_PSOC6
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bool "PSoC-6 MCU SCB spi driver"
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depends on SOC_FAMILY_PSOC6
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help
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This option enables the SCB[SPI] driver for PSoC-6 SoC family.
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421
drivers/spi/spi_psoc6.c
Normal file
421
drivers/spi/spi_psoc6.c
Normal file
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@ -0,0 +1,421 @@
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/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright (c) 2017, NXP
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* Copyright (c) 2021, ATL Electronics.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT cypress_psoc6_spi
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#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(spi_psoc6);
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#include <errno.h>
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#include <drivers/spi.h>
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#include <soc.h>
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#include "spi_context.h"
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#include "cy_syslib.h"
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#include "cy_sysclk.h"
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#include "cy_scb_spi.h"
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#include "cy_sysint.h"
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#define SPI_CHIP_SELECT_COUNT 4
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#define SPI_MAX_DATA_WIDTH 16
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#define SPI_PSOC6_CLK_DIV_NUMBER 1
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struct spi_psoc6_config {
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CySCB_Type *base;
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uint32_t periph_id;
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void (*irq_config_func)(const struct device *dev);
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uint32_t num_pins;
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struct soc_gpio_pin pins[];
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};
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struct spi_psoc6_transfer {
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uint8_t *txData;
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uint8_t *rxData;
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size_t dataSize;
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};
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struct spi_psoc6_data {
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struct spi_context ctx;
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struct cy_stc_scb_spi_config cfg;
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struct spi_psoc6_transfer xfer;
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};
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static void spi_psoc6_transfer_next_packet(const struct device *dev)
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{
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const struct spi_psoc6_config *config = dev->config;
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struct spi_psoc6_data *data = dev->data;
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struct spi_context *ctx = &data->ctx;
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struct spi_psoc6_transfer *xfer = &data->xfer;
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uint32_t count;
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LOG_DBG("TX L: %d, RX L: %d", ctx->tx_len, ctx->rx_len);
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if ((ctx->tx_len == 0U) && (ctx->rx_len == 0U)) {
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/* nothing left to rx or tx, we're done! */
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xfer->dataSize = 0U;
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spi_context_cs_control(ctx, false);
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spi_context_complete(ctx, 0U);
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return;
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}
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if (ctx->tx_len == 0U) {
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/* rx only, nothing to tx */
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xfer->txData = NULL;
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xfer->rxData = ctx->rx_buf;
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xfer->dataSize = ctx->rx_len;
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} else if (ctx->rx_len == 0U) {
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/* tx only, nothing to rx */
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xfer->txData = (uint8_t *) ctx->tx_buf;
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xfer->rxData = NULL;
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xfer->dataSize = ctx->tx_len;
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} else if (ctx->tx_len == ctx->rx_len) {
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/* rx and tx are the same length */
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xfer->txData = (uint8_t *) ctx->tx_buf;
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xfer->rxData = ctx->rx_buf;
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xfer->dataSize = ctx->tx_len;
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} else if (ctx->tx_len > ctx->rx_len) {
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/* Break up the tx into multiple transfers so we don't have to
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* rx into a longer intermediate buffer. Leave chip select
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* active between transfers.
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*/
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xfer->txData = (uint8_t *) ctx->tx_buf;
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xfer->rxData = ctx->rx_buf;
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xfer->dataSize = ctx->rx_len;
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} else {
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/* Break up the rx into multiple transfers so we don't have to
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* tx from a longer intermediate buffer. Leave chip select
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* active between transfers.
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*/
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xfer->txData = (uint8_t *) ctx->tx_buf;
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xfer->rxData = ctx->rx_buf;
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xfer->dataSize = ctx->tx_len;
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}
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if (xfer->txData != NULL) {
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if (Cy_SCB_SPI_WriteArray(config->base, xfer->txData,
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xfer->dataSize) != xfer->dataSize) {
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goto err;
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}
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} else {
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/* Need fill TX fifo with garbage to perform read.
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* This keeps logic simple and saves stack.
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* Use 0 as dummy data.
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*/
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for (count = 0U; count < xfer->dataSize; count++) {
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if (Cy_SCB_SPI_Write(config->base, 0U) == 0U) {
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goto err;
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}
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}
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}
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LOG_DBG("TRX L: %d", xfer->dataSize);
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return;
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err:
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/* no FIFO available to run the transfer */
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xfer->dataSize = 0U;
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spi_context_cs_control(ctx, false);
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spi_context_complete(ctx, -ENOMEM);
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}
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static void spi_psoc6_isr(const struct device *dev)
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{
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const struct spi_psoc6_config *config = dev->config;
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struct spi_psoc6_data *data = dev->data;
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Cy_SCB_ClearMasterInterrupt(config->base,
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CY_SCB_MASTER_INTR_SPI_DONE);
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/* extract data from RX FIFO */
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if (data->xfer.rxData != NULL) {
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Cy_SCB_SPI_ReadArray(config->base,
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data->xfer.rxData,
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data->xfer.dataSize);
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} else {
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Cy_SCB_ClearRxFifo(config->base);
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}
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/* Set next data block */
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spi_context_update_tx(&data->ctx, 1, data->xfer.dataSize);
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spi_context_update_rx(&data->ctx, 1, data->xfer.dataSize);
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/* Start next block
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* Since 1 byte at TX FIFO will start transfer data, let's try
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* minimize ISR recursion disabling all interrupt sources when add
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* data on TX FIFO
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*/
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Cy_SCB_SetMasterInterruptMask(config->base, 0U);
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spi_psoc6_transfer_next_packet(dev);
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if (data->xfer.dataSize > 0U) {
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Cy_SCB_SetMasterInterruptMask(config->base,
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CY_SCB_MASTER_INTR_SPI_DONE);
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}
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}
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static uint32_t spi_psoc6_get_freqdiv(uint32_t frequency)
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{
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uint32_t oversample;
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uint32_t bus_freq = 100000000UL;
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/*
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* TODO: Get PerBusSpeed when clocks are available to PSoC-6.
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* Currently the bus freq is fixed to 50Mhz and max SPI clk can be
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* 12.5MHz.
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*/
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for (oversample = 4; oversample < 16; oversample++) {
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if ((bus_freq / oversample) <= frequency) {
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break;
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}
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}
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/* Oversample [4, 16] */
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return oversample;
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}
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static void spi_psoc6_master_get_defaults(struct cy_stc_scb_spi_config *cfg)
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{
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cfg->spiMode = CY_SCB_SPI_MASTER;
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cfg->subMode = CY_SCB_SPI_MOTOROLA;
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cfg->sclkMode = 0U;
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cfg->oversample = 0U;
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cfg->rxDataWidth = 0U;
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cfg->txDataWidth = 0U;
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cfg->enableMsbFirst = false;
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cfg->enableFreeRunSclk = false;
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cfg->enableInputFilter = false;
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cfg->enableMisoLateSample = false;
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cfg->enableTransferSeperation = false;
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cfg->ssPolarity = 0U;
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cfg->enableWakeFromSleep = false;
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cfg->rxFifoTriggerLevel = 0U;
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cfg->rxFifoIntEnableMask = 0U;
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cfg->txFifoTriggerLevel = 0U;
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cfg->txFifoIntEnableMask = 0U;
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cfg->masterSlaveIntEnableMask = 0U;
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}
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static int spi_psoc6_configure(const struct device *dev,
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const struct spi_config *spi_cfg)
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{
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struct spi_psoc6_data *data = dev->data;
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uint32_t word_size;
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if (spi_context_configured(&data->ctx, spi_cfg)) {
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/* This configuration is already in use */
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return 0;
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}
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word_size = SPI_WORD_SIZE_GET(spi_cfg->operation);
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if (word_size > SPI_MAX_DATA_WIDTH) {
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LOG_ERR("Word size %d is greater than %d",
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word_size, SPI_MAX_DATA_WIDTH);
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return -EINVAL;
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}
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if (SPI_OP_MODE_GET(spi_cfg->operation) == SPI_OP_MODE_MASTER) {
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spi_psoc6_master_get_defaults(&data->cfg);
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if (spi_cfg->slave > SPI_CHIP_SELECT_COUNT) {
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LOG_ERR("Slave %d is greater than %d",
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spi_cfg->slave, SPI_CHIP_SELECT_COUNT);
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return -EINVAL;
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}
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data->cfg.rxDataWidth = data->cfg.txDataWidth = word_size;
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if (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPHA) {
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if (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPOL) {
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data->cfg.sclkMode = CY_SCB_SPI_CPHA1_CPOL1;
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} else {
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data->cfg.sclkMode = CY_SCB_SPI_CPHA1_CPOL0;
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}
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} else {
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if (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPOL) {
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data->cfg.sclkMode = CY_SCB_SPI_CPHA0_CPOL1;
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} else {
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data->cfg.sclkMode = CY_SCB_SPI_CPHA0_CPOL0;
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}
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}
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data->cfg.enableMsbFirst = !!!(spi_cfg->operation &
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SPI_TRANSFER_LSB);
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data->cfg.oversample = spi_psoc6_get_freqdiv(spi_cfg->frequency);
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data->ctx.config = spi_cfg;
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spi_context_cs_configure(&data->ctx);
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} else {
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/* Slave mode is not implemented yet. */
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return -ENOTSUP;
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}
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return 0;
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}
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static void spi_psoc6_transceive_sync_loop(const struct device *dev)
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{
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const struct spi_psoc6_config *config = dev->config;
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struct spi_psoc6_data *data = dev->data;
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while (data->xfer.dataSize > 0U) {
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while (!Cy_SCB_IsTxComplete(config->base)) {
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;
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}
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if (data->xfer.rxData != NULL) {
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Cy_SCB_SPI_ReadArray(config->base,
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data->xfer.rxData,
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data->xfer.dataSize);
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} else {
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Cy_SCB_ClearRxFifo(config->base);
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}
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spi_context_update_tx(&data->ctx, 1, data->xfer.dataSize);
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spi_context_update_rx(&data->ctx, 1, data->xfer.dataSize);
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spi_psoc6_transfer_next_packet(dev);
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}
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}
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static int spi_psoc6_transceive(const struct device *dev,
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const struct spi_config *spi_cfg,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs,
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bool asynchronous,
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struct k_poll_signal *signal)
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{
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const struct spi_psoc6_config *config = dev->config;
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struct spi_psoc6_data *data = dev->data;
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int ret;
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spi_context_lock(&data->ctx, asynchronous, signal, spi_cfg);
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LOG_DBG("\n\n");
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ret = spi_psoc6_configure(dev, spi_cfg);
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if (ret) {
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goto out;
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}
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Cy_SCB_SPI_Init(config->base, &data->cfg, NULL);
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Cy_SCB_SPI_SetActiveSlaveSelect(config->base, spi_cfg->slave);
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Cy_SCB_SPI_Enable(config->base);
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spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
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spi_context_cs_control(&data->ctx, true);
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spi_psoc6_transfer_next_packet(dev);
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if (asynchronous) {
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Cy_SCB_SetMasterInterruptMask(config->base,
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CY_SCB_MASTER_INTR_SPI_DONE);
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} else {
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spi_psoc6_transceive_sync_loop(dev);
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}
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ret = spi_context_wait_for_completion(&data->ctx);
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Cy_SCB_SPI_Disable(config->base, NULL);
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out:
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spi_context_release(&data->ctx, ret);
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return ret;
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}
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||||||
|
static int spi_psoc6_transceive_sync(const struct device *dev,
|
||||||
|
const struct spi_config *spi_cfg,
|
||||||
|
const struct spi_buf_set *tx_bufs,
|
||||||
|
const struct spi_buf_set *rx_bufs)
|
||||||
|
{
|
||||||
|
return spi_psoc6_transceive(dev, spi_cfg, tx_bufs,
|
||||||
|
rx_bufs, false, NULL);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef CONFIG_SPI_ASYNC
|
||||||
|
static int spi_psoc6_transceive_async(const struct device *dev,
|
||||||
|
const struct spi_config *spi_cfg,
|
||||||
|
const struct spi_buf_set *tx_bufs,
|
||||||
|
const struct spi_buf_set *rx_bufs,
|
||||||
|
struct k_poll_signal *async)
|
||||||
|
{
|
||||||
|
return spi_psoc6_transceive(dev, spi_cfg, tx_bufs,
|
||||||
|
rx_bufs, true, async);
|
||||||
|
}
|
||||||
|
#endif /* CONFIG_SPI_ASYNC */
|
||||||
|
|
||||||
|
static int spi_psoc6_release(const struct device *dev,
|
||||||
|
const struct spi_config *config)
|
||||||
|
{
|
||||||
|
struct spi_psoc6_data *data = dev->data;
|
||||||
|
|
||||||
|
spi_context_unlock_unconditionally(&data->ctx);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int spi_psoc6_init(const struct device *dev)
|
||||||
|
{
|
||||||
|
const struct spi_psoc6_config *config = dev->config;
|
||||||
|
|
||||||
|
soc_gpio_list_configure(config->pins, config->num_pins);
|
||||||
|
|
||||||
|
Cy_SysClk_PeriphAssignDivider(config->periph_id,
|
||||||
|
CY_SYSCLK_DIV_8_BIT,
|
||||||
|
SPI_PSOC6_CLK_DIV_NUMBER);
|
||||||
|
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT,
|
||||||
|
SPI_PSOC6_CLK_DIV_NUMBER, 0U);
|
||||||
|
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT,
|
||||||
|
SPI_PSOC6_CLK_DIV_NUMBER);
|
||||||
|
|
||||||
|
#ifdef CONFIG_SPI_ASYNC
|
||||||
|
config->irq_config_func(dev);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return spi_psoc6_release(dev, NULL);
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct spi_driver_api spi_psoc6_driver_api = {
|
||||||
|
.transceive = spi_psoc6_transceive_sync,
|
||||||
|
#ifdef CONFIG_SPI_ASYNC
|
||||||
|
.transceive_async = spi_psoc6_transceive_async,
|
||||||
|
#endif
|
||||||
|
.release = spi_psoc6_release,
|
||||||
|
};
|
||||||
|
|
||||||
|
#define SPI_PSOC6_DEVICE_INIT(n) \
|
||||||
|
static void spi_psoc6_spi##n##_irq_cfg(const struct device *port); \
|
||||||
|
static const struct spi_psoc6_config spi_psoc6_config_##n = { \
|
||||||
|
.base = (CySCB_Type *)DT_INST_REG_ADDR(n), \
|
||||||
|
.periph_id = DT_INST_PROP(n, peripheral_id), \
|
||||||
|
.num_pins = CY_PSOC6_DT_INST_NUM_PINS(n), \
|
||||||
|
.pins = CY_PSOC6_DT_INST_PINS(n), \
|
||||||
|
.irq_config_func = spi_psoc6_spi##n##_irq_cfg, \
|
||||||
|
}; \
|
||||||
|
static struct spi_psoc6_data spi_psoc6_dev_data_##n = { \
|
||||||
|
SPI_CONTEXT_INIT_LOCK(spi_psoc6_dev_data_##n, ctx), \
|
||||||
|
SPI_CONTEXT_INIT_SYNC(spi_psoc6_dev_data_##n, ctx), \
|
||||||
|
}; \
|
||||||
|
DEVICE_DT_INST_DEFINE(n, &spi_psoc6_init, NULL, \
|
||||||
|
&spi_psoc6_dev_data_##n, \
|
||||||
|
&spi_psoc6_config_##n, POST_KERNEL, \
|
||||||
|
CONFIG_SPI_INIT_PRIORITY, \
|
||||||
|
&spi_psoc6_driver_api); \
|
||||||
|
static void spi_psoc6_spi##n##_irq_cfg(const struct device *port) \
|
||||||
|
{ \
|
||||||
|
CY_PSOC6_DT_INST_NVIC_INSTALL(n, \
|
||||||
|
spi_psoc6_isr); \
|
||||||
|
};
|
||||||
|
|
||||||
|
DT_INST_FOREACH_STATUS_OKAY(SPI_PSOC6_DEVICE_INIT)
|
||||||
|
|
@ -248,6 +248,97 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
spi0: spi@40610000 {
|
||||||
|
compatible = "cypress,psoc6-spi";
|
||||||
|
reg = <0x40610000 0x10000>;
|
||||||
|
interrupts = <41 7>;
|
||||||
|
peripheral-id = <0>;
|
||||||
|
status = "disabled";
|
||||||
|
label = "spi_0";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
};
|
||||||
|
spi1: spi@40620000 {
|
||||||
|
compatible = "cypress,psoc6-spi";
|
||||||
|
reg = <0x40620000 0x10000>;
|
||||||
|
interrupts = <42 7>;
|
||||||
|
peripheral-id = <1>;
|
||||||
|
status = "disabled";
|
||||||
|
label = "spi_1";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
};
|
||||||
|
spi2: spi@40630000 {
|
||||||
|
compatible = "cypress,psoc6-spi";
|
||||||
|
reg = <0x40630000 0x10000>;
|
||||||
|
interrupts = <43 7>;
|
||||||
|
peripheral-id = <2>;
|
||||||
|
status = "disabled";
|
||||||
|
label = "spi_2";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
};
|
||||||
|
spi3: spi@40640000 {
|
||||||
|
compatible = "cypress,psoc6-spi";
|
||||||
|
reg = <0x40640000 0x10000>;
|
||||||
|
interrupts = <44 7>;
|
||||||
|
peripheral-id = <3>;
|
||||||
|
status = "disabled";
|
||||||
|
label = "spi_3";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
};
|
||||||
|
spi4: spi@40650000 {
|
||||||
|
compatible = "cypress,psoc6-spi";
|
||||||
|
reg = <0x40650000 0x10000>;
|
||||||
|
interrupts = <45 7>;
|
||||||
|
peripheral-id = <4>;
|
||||||
|
status = "disabled";
|
||||||
|
label = "spi_4";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
};
|
||||||
|
spi5: spi@40660000 {
|
||||||
|
compatible = "cypress,psoc6-spi";
|
||||||
|
reg = <0x40660000 0x10000>;
|
||||||
|
interrupts = <46 7>;
|
||||||
|
peripheral-id = <5>;
|
||||||
|
status = "disabled";
|
||||||
|
label = "spi_5";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
};
|
||||||
|
spi6: spi@40670000 {
|
||||||
|
compatible = "cypress,psoc6-spi";
|
||||||
|
reg = <0x40670000 0x10000>;
|
||||||
|
interrupts = <47 7>;
|
||||||
|
peripheral-id = <6>;
|
||||||
|
status = "disabled";
|
||||||
|
label = "spi_6";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
};
|
||||||
|
spi7: spi@40680000 {
|
||||||
|
compatible = "cypress,psoc6-spi";
|
||||||
|
reg = <0x40680000 0x10000>;
|
||||||
|
interrupts = <48 7>;
|
||||||
|
peripheral-id = <7>;
|
||||||
|
status = "disabled";
|
||||||
|
label = "spi_7";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
};
|
||||||
|
spi8: spi@40690000 {
|
||||||
|
compatible = "cypress,psoc6-spi";
|
||||||
|
reg = <0x40690000 0x10000>;
|
||||||
|
interrupts = <18 7>;
|
||||||
|
peripheral-id = <8>;
|
||||||
|
status = "disabled";
|
||||||
|
label = "spi_8";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
};
|
||||||
|
|
||||||
uart0: uart@40610000 {
|
uart0: uart@40610000 {
|
||||||
compatible = "cypress,psoc6-uart";
|
compatible = "cypress,psoc6-uart";
|
||||||
reg = <0x40610000 0x10000>;
|
reg = <0x40610000 0x10000>;
|
||||||
|
|
|
||||||
|
|
@ -21,6 +21,10 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||||
|
|
||||||
source "soc/arm/cypress/psoc6/Kconfig.defconfig.psoc*"
|
source "soc/arm/cypress/psoc6/Kconfig.defconfig.psoc*"
|
||||||
|
|
||||||
|
config SPI_PSOC6
|
||||||
|
default y
|
||||||
|
depends on SPI
|
||||||
|
|
||||||
config UART_PSOC6
|
config UART_PSOC6
|
||||||
default y
|
default y
|
||||||
depends on SERIAL
|
depends on SERIAL
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue