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esp32: drivers: spi_flash: add host flash support

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Add support for ESP32 host flash chip

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
This commit is contained in:
Glauber Maroto Ferreira 2021-02-26 12:04:09 -03:00 • committed by Anas Nashif
commit d8f6e66588
10 changed files with 685 additions and 1 deletions
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7
soc/xtensa/esp32/linker.ld
View file

@ -40,6 +40,10 @@ PROVIDE ( Cache_Read_Disable_rom = 0x40009ab8 );
PROVIDE ( Cache_Read_Enable_rom = 0x40009a84 );
PROVIDE ( Cache_Read_Init_rom = 0x40009950 );
PROVIDE ( phy_get_romfuncs = 0x40004100 );
PROVIDE ( esp_rom_spiflash_read_user_cmd = 0x400621b0 );
PROVIDE ( g_rom_spiflash_dummy_len_plus = 0x3ffae290 );
PROVIDE ( g_rom_flashchip = 0x3ffae270 );
PROVIDE ( SPI0 = 0x3ff43000 );
PROVIDE ( SPI1 = 0x3ff42fff );
PROVIDE ( SPI2 = 0x3ff64fff );
PROVIDE ( SPI3 = 0x3ff65fff );
@ -269,6 +273,7 @@ _net_buf_pool_list = _esp_net_buf_pool_list;
*libzephyr.a:log_core.*(.rodata .rodata.*)
*libzephyr.a:log_backend_uart.*(.rodata .rodata.*)
*libzephyr.a:log_output.*(.rodata .rodata.*)
*libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*)
*libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)
. = ALIGN(4);
@ -380,7 +385,7 @@ __shell_root_cmds_end = __esp_shell_root_cmds_end;
*libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)
*libhal.a:(.literal .text .literal.* .text.*)
*libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)
*libzephyr.a:spi_flash_rom_patch.*(.literal .text .literal.* .text.*)
*libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)
*libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)
*libzephyr.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)
*libzephyr.a:log_core.*(.literal .text .literal.* .text.*)

4
soc/xtensa/esp32/soc.c
View file

@ -21,6 +21,7 @@
#include "hal/soc_ll.h"
#include "soc/cpu.h"
#include "soc/gpio_periph.h"
#include "esp_spi_flash.h"
extern void z_cstart(void);
@ -95,6 +96,9 @@ void __attribute__((section(".iram1"))) __start(void)
*wdt_rtc_protect = 0;
#endif
#if CONFIG_SOC_FLASH_ESP32
spi_flash_guard_set(&g_flash_guard_default_ops);
#endif
/* Start Zephyr */
z_cstart();

5
soc/xtensa/esp32/soc.h
View file

@ -9,6 +9,7 @@
#include <soc/dport_reg.h>
#include <soc/rtc_cntl_reg.h>
#include <esp32/rom/ets_sys.h>
#include <esp32/rom/spi_flash.h>
#include <zephyr/types.h>
#include <stdbool.h>
@ -45,4 +46,8 @@ extern void esp32_rom_ets_set_appcpu_boot_addr(void *addr);
extern uint8_t esp32_rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add);
extern void esp32_rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
/* ROM information related to SPI Flash chip timing and device */
extern esp_rom_spiflash_chip_t g_rom_flashchip;
extern uint8_t g_rom_spiflash_dummy_len_plus[];
#endif /* __SOC_H__ */