soc: nxp: imxrt: add imxrt118x series and update related files

Add new RT118x device, due to structure is different from rt11xx series.
Boot header also differ from rt10xx and rt11xx, so add support for boot
container.

define new container name and new container tag

Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>

include/zephyr/linker/section_tags.h

@@ -44,6 +44,7 @@
 #define __imx_boot_data_section Z_GENERIC_SECTION(_IMX_BOOT_DATA_SECTION_NAME)
 #define __imx_boot_ivt_section Z_GENERIC_SECTION(_IMX_BOOT_IVT_SECTION_NAME)
 #define __imx_boot_dcd_section Z_GENERIC_SECTION(_IMX_BOOT_DCD_SECTION_NAME)
+#define __imx_boot_container_section Z_GENERIC_SECTION(_IMX_BOOT_CONTAINER_SECTION_NAME)
 #define __stm32_sdram1_section Z_GENERIC_SECTION(_STM32_SDRAM1_SECTION_NAME)
 #define __stm32_sdram2_section Z_GENERIC_SECTION(_STM32_SDRAM2_SECTION_NAME)
 #define __stm32_backup_sram_section Z_GENERIC_SECTION(_STM32_BACKUP_SRAM_SECTION_NAME)

include/zephyr/linker/sections.h

@@ -67,6 +67,7 @@
 #define _IMX_BOOT_DATA_SECTION_NAME	.boot_hdr.data
 #define _IMX_BOOT_IVT_SECTION_NAME	.boot_hdr.ivt
 #define _IMX_BOOT_DCD_SECTION_NAME	.boot_hdr.dcd_data
+#define _IMX_BOOT_CONTAINER_SECTION_NAME .boot_hdr.container
 
 #define _STM32_SDRAM1_SECTION_NAME	.stm32_sdram1
 #define _STM32_SDRAM2_SECTION_NAME	.stm32_sdram2

soc/nxp/imxrt/CMakeLists.txt

@@ -37,6 +37,24 @@ if(CONFIG_SOC_SERIES_IMXRT10XX OR CONFIG_SOC_SERIES_IMXRT11XX)
   zephyr_compile_definitions(XIP_EXTERNAL_FLASH)
 endif()
 
+if(CONFIG_SOC_SERIES_IMXRT118X)
+  zephyr_linker_section_configure(
+    SECTION .rom_start
+    INPUT ".boot_hdr.conf"
+    OFFSET ${CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET}
+    KEEP
+    PRIO 10
+  )
+  zephyr_linker_section_configure(
+    SECTION .rom_start
+    INPUT ".boot_hdr.container"
+    OFFSET ${CONFIG_IMAGE_CONTAINER_OFFSET}
+    KEEP
+    PRIO 11
+  )
+  zephyr_compile_definitions(XIP_EXTERNAL_FLASH)
+endif()
+
 if(CONFIG_SOC_SERIES_IMXRT6XX OR CONFIG_SOC_SERIES_IMXRT5XX)
   zephyr_linker_sources_ifdef(CONFIG_USB_DEVICE_DRIVER SECTIONS usb.ld)
   zephyr_linker_sources_ifdef(CONFIG_UDC_DRIVER SECTIONS usb.ld)
@@ -45,3 +63,7 @@ endif()
 if(CONFIG_MEMC)
   zephyr_library_include_directories(${ZEPHYR_BASE}/drivers/memc)
 endif()
+
+if(CONFIG_SOC_SERIES_IMXRT118X)
+  zephyr_linker_sources_ifdef(CONFIG_SOC_SERIES_IMXRT118X SECTIONS container.ld)
+endif()

soc/nxp/imxrt/Kconfig

@@ -29,6 +29,7 @@ if FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI
 
 choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET
 	prompt "FlexSPI drivers relocation target"
+	default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM if SOC_MIMXRT1189_CM33 # RT118X_CM33 core lacks ITCM
 	default FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM
 	help
 	  Select the location to run the FlexSPI drivers when using
@@ -96,6 +97,28 @@ config FLEXSPI_CONFIG_BLOCK_OFFSET
 	  sequence (optional), etc. The boot ROM expects FlexSPI configuration
 	  parameter to be presented in serial nor flash.
 
+config IMAGE_CONTAINER_OFFSET
+	hex "Image container"
+	default 0x1000
+	depends on SOC_SERIES_IMXRT118X
+	help
+	  Image container is a boot image format that is used by ROM. Container
+	  format consists container header, image arrary entry, signature block
+	  and user program images and data. The boot ROM expects container data
+	  to be saved in external memory.
+
+# Note- This config present the offest between container header and user
+# image. If ROM_START_OFFSET changed, you also need to change CONTAINER_USER_IMAGE_OFFSET
+# value. CONTAINER_USER_IMAGE_OFFSET = ROM_START_OFFSET - IMAGE_CONTAINER_OFFSET.
+config CONTAINER_USER_IMAGE_OFFSET
+	hex "The offset between container header and user image"
+	default 0xA000
+	depends on SOC_SERIES_IMXRT118X
+	help
+	  The offset between container and user image. IF change the user image
+	  start address, please don't forget to modify CONTAINER_USER_IMAGE_OFFSET
+	  value, this will make ROM could get the user image start address.
+
 config IMAGE_VECTOR_TABLE_OFFSET
 	hex "Image vector table offset"
 	default 0x1000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR
@@ -113,7 +136,6 @@ config DEVICE_CONFIGURATION_DATA
 	  useful if your application expects components like SDRAM to be
 	  initialized at boot time.
 
-
 config EXTERNAL_MEM_CONFIG_DATA
 	bool "External Memory Configuration Data"
 	depends on !DEVICE_CONFIGURATION_DATA
@@ -171,12 +193,11 @@ config SECOND_CORE_MCUX
 	  generated header specifying the VMA and LMA of each memory section
 	  to load
 
-
 config FLEXSPI_CONFIG_BLOCK_OFFSET
 	hex
-	default 0x400 if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX
+	default 0x400 if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX || SOC_SERIES_IMXRT118X
 
-if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX
+if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX || SOC_SERIES_IMXRT118X
 
 config PM_MCUX_GPC
 	bool "MCUX general power controller driver"
@@ -206,6 +227,6 @@ config INIT_ENET_PLL
 config INIT_SYS_PLL
 	bool "Initialize System PLL"
 
-endif # SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX
+endif # SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX || SOC_SERIES_IMXRT118X
 
 endif # SOC_FAMILY_NXP_IMXRT

soc/nxp/imxrt/Kconfig.defconfig

@@ -7,7 +7,7 @@ if SOC_FAMILY_NXP_IMXRT
 # can override the defaults given here
 rsource "*/Kconfig.defconfig"
 
-if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX
+if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX || SOC_SERIES_IMXRT118X
 
 config SERIAL_INIT_PRIORITY
 	default 55 if SERIAL
@@ -15,6 +15,7 @@ config SERIAL_INIT_PRIORITY
 
 config ROM_START_OFFSET
 	default 0x400 if BOOTLOADER_MCUBOOT
+	default 0xb000 if BOOT_FLEXSPI_NOR && SOC_SERIES_IMXRT118X
 	default 0x2000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR
 
 config PINCTRL_IMX
@@ -75,7 +76,7 @@ config SYSTEM_WORKQUEUE_STACK_SIZE
 endif # ETH_NXP_ENET
 
 config MEMC
-	default y
+	default y if !SOC_SERIES_IMXRT118X # RT118X lacks FLEXRAM
 
 choice USB_MCUX_CONTROLLER_TYPE
 	default USB_DC_NXP_EHCI
@@ -116,7 +117,7 @@ endif # MBEDTLS
 config CACHE_MANAGEMENT
 	default y if CPU_CORTEX_M7
 
-endif # SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX
+endif # SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX || SOC_SERIES_IMXRT118X
 
 # Logic to set flash size for all IMXRT parts
 DT_CHOSEN_Z_FLASH := zephyr,flash

soc/nxp/imxrt/boot_header.ld

@@ -4,15 +4,25 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#if defined(CONFIG_SOC_SERIES_IMXRT118X)
+__VECTOR_TABLE = CONFIG_ROM_START_OFFSET;
+__Vectors = __VECTOR_TABLE;
+#endif
+
 . = CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET;
-#if defined(CONFIG_SOC_SERIES_IMXRT11XX) || defined(CONFIG_SOC_SERIES_IMXRT10XX)
+#if defined(CONFIG_SOC_SERIES_IMXRT11XX) || defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT118X)
 KEEP(*(.boot_hdr.conf))
 #endif
 #if defined(CONFIG_SOC_SERIES_IMXRT6XX) || defined(CONFIG_SOC_SERIES_IMXRT5XX)
 KEEP(*(.flash_conf))
 #endif
+#if defined(CONFIG_SOC_SERIES_IMXRT118X)
+. = CONFIG_IMAGE_CONTAINER_OFFSET;
+KEEP(*(.boot_hdr.container))
+#else
 . = CONFIG_IMAGE_VECTOR_TABLE_OFFSET;
 KEEP(*(.boot_hdr.ivt))
+#endif
 #if defined(CONFIG_SOC_SERIES_IMXRT11XX) || defined(CONFIG_SOC_SERIES_IMXRT10XX)
 KEEP(*(.boot_hdr.data))
 #ifdef CONFIG_DEVICE_CONFIGURATION_DATA

soc/nxp/imxrt/container.ld

@@ -0,0 +1,10 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#if defined(CONFIG_SOC_SERIES_IMXRT118X) && CONFIG_NXP_IMXRT_BOOT_HEADER
+__CONTAINER_IMG_OFFSET = CONFIG_CONTAINER_USER_IMAGE_OFFSET;
+__CONTAINER_IMG_SIZE = _flash_used;
+#endif

soc/nxp/imxrt/imxrt118x/CMakeLists.txt

@@ -0,0 +1,11 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_sources(soc.c)
+
+zephyr_include_directories(.)
+
+set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

soc/nxp/imxrt/imxrt118x/Kconfig

@@ -0,0 +1,52 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_IMXRT118X
+	select CPU_CORTEX_M_HAS_DWT
+	select PLATFORM_SPECIFIC_INIT
+	select INIT_ARCH_HW_AT_BOOT if SOC_MIMXRT1189_CM33
+	select ARM
+	select CLOCK_CONTROL
+	select HAS_MCUX_CACHE
+	select ARMV8_M_DSP if SOC_MIMXRT1189_CM33
+	select CPU_HAS_ARM_SAU if SOC_MIMXRT1189_CM33
+	select HAS_MCUX
+	select CPU_HAS_ARM_MPU
+	select INIT_ARM_PLL
+	select ARM_TRUSTZONE_M if SOC_MIMXRT1189_CM33
+	select CPU_HAS_ICACHE if SOC_MIMXRT1189_CM7
+	select CPU_HAS_DCACHE if SOC_MIMXRT1189_CM7
+	select CPU_HAS_FPU
+	select CPU_HAS_FPU_DOUBLE_PRECISION if SOC_MIMXRT1189_CM7
+	select HAS_MCUX_IOMUXC
+	select HAS_SWO
+
+config SOC_MIMXRT1189_CM33
+	select CPU_CORTEX_M33
+
+config SOC_MIMXRT1189_CM7
+	select CPU_CORTEX_M7
+
+if SOC_SERIES_IMXRT118X
+
+config MCUX_CORE_SUFFIX
+	default "_cm7" if SOC_MIMXRT1189_CM7
+	default "_cm33" if SOC_MIMXRT1189_CM33
+
+config TRDC_MCUX_TRDC
+	default y
+	bool "Use TRDC MCUX Driver"
+
+config S3MU_MCUX_S3MU
+	default y
+	bool "Use S3MU MCUX Driver"
+
+config IMXRT118X_CM33_XCACHE_PS
+	bool "Use CM33 XCACHE_PS"
+	default y if SOC_MIMXRT1189_CM33
+	help
+	  Use CM33 XCACHE_PS at boot. Please note XCACHE_PC have been
+	  enabled in SystemInit function. If this Kconfig is cleared,
+	  the XCACHE controller won't be enabled during SOC init
+
+endif # SOC_SERIES_IMXRT118X

soc/nxp/imxrt/imxrt118x/Kconfig.defconfig

@@ -0,0 +1,34 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_IMXRT118X
+
+config NUM_IRQS
+	default 239
+
+config GPIO
+	default y
+
+if CORTEX_M_SYSTICK
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 240000000 if SOC_MIMXRT1189_CM33
+	default 792000000 if SOC_MIMXRT1189_CM7
+
+endif # CORTEX_M_SYSTICK
+
+config DCDC_VALUE
+	default 0x13
+
+config FLEXSPI_CONFIG_BLOCK_OFFSET
+	default 0x400 if BOOT_FLEXSPI_NOR
+
+if SECOND_CORE_MCUX
+
+# RT Boot header is only needed on primary core
+config NXP_IMXRT_BOOT_HEADER
+	default y
+	depends on !(CPU_CORTEX_M7 || BOOTLOADER_MCUBOOT)
+
+endif
+endif

soc/nxp/imxrt/imxrt118x/Kconfig.soc

@@ -0,0 +1,62 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_IMXRT118X
+	bool
+	select SOC_FAMILY_NXP_IMXRT
+
+config SOC_SERIES
+	default "imxrt118x" if SOC_SERIES_IMXRT118X
+
+config SOC_MIMXRT1189
+	bool
+	select SOC_SERIES_IMXRT118X
+
+config SOC_MIMXRT1189_CM33
+	bool
+	select SOC_MIMXRT1189
+
+config SOC_MIMXRT1189_CM7
+	bool
+	select SOC_MIMXRT1189
+
+config SOC
+	default "mimxrt1189" if SOC_MIMXRT1189
+
+config SOC_PART_NUMBER_MIMXRT1189CVM8B
+	bool
+
+config SOC_PART_NUMBER_MIMXRT1189XVM8B
+	bool
+
+config SOC_PART_NUMBER_MIMXRT1187AVM8B
+	bool
+
+config SOC_PART_NUMBER_MIMXRT1187CVM8B
+	bool
+
+config SOC_PART_NUMBER_MIMXRT1187XVM8B
+	bool
+
+config SOC_PART_NUMBER_MIMXRT1182CVP2B
+	bool
+
+config SOC_PART_NUMBER_MIMXRT1182XVP2B
+	bool
+
+config SOC_PART_NUMBER_MIMXRT1181CVP2B
+	bool
+
+config SOC_PART_NUMBER_MIMXRT1181XVP2B
+	bool
+
+config SOC_PART_NUMBER
+	default "MIMXRT1189CVM8B" if SOC_PART_NUMBER_MIMXRT1189CVM8B
+	default "MIMXRT1189XVM8B" if SOC_PART_NUMBER_MIMXRT1189XVM8B
+	default "MIMXRT1187AVM8B" if SOC_PART_NUMBER_MIMXRT1187AVM8B
+	default "MIMXRT1187CVM8B" if SOC_PART_NUMBER_MIMXRT1187CVM8B
+	default "MIMXRT1187XVM8B" if SOC_PART_NUMBER_MIMXRT1187XVM8B
+	default "MIMXRT1182CVP2B" if SOC_PART_NUMBER_MIMXRT1182CVP2B
+	default "MIMXRT1182XVP2B" if SOC_PART_NUMBER_MIMXRT1182XVP2B
+	default "MIMXRT1181CVP2B" if SOC_PART_NUMBER_MIMXRT1181CVP2B
+	default "MIMXRT1181XVP2B" if SOC_PART_NUMBER_MIMXRT1181XVP2B

soc/nxp/imxrt/imxrt118x/linker.ld

@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2014 Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/devicetree.h>
+
+
+#define IS_CHOSEN_SRAM(x) (DT_DEP_ORD(DT_NODELABEL(x)) == DT_DEP_ORD(DT_CHOSEN(zephyr_sram)))
+
+MEMORY
+     {
+
+#if (DT_REG_SIZE(DT_NODELABEL(sdram0)) > 0) && !IS_CHOSEN_SRAM(sdram0)
+        SDRAM  (wx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(sdram0)), LENGTH = DT_REG_SIZE(DT_NODELABEL(sdram0))
+#endif
+
+     }
+
+#include <zephyr/arch/arm/cortex_m/scripts/linker.ld>

soc/nxp/imxrt/imxrt118x/pinctrl_soc.h

@@ -0,0 +1,123 @@
+/*
+ * Copyright 2024, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_RT118X_H_
+#define ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_RT118X_H_
+
+#include <zephyr/devicetree.h>
+#include <zephyr/types.h>
+#include "fsl_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MCUX_IMX_ODE_SHIFT 4
+#define MCUX_IMX_PUS_SHIFT 3
+#define MCUX_IMX_PUE_SHIFT 2
+#define MCUX_IMX_DSE_SHIFT 1
+#define MCUX_IMX_SRE_SHIFT 0
+#define MCUX_IMX_PULL_SHIFT 2
+#define MCUX_IMX_PULL_PULLDOWN 0x2
+#define MCUX_IMX_PULL_PULLUP 0x1
+#define MCUX_IMX_PDRV_SHIFT 1
+#define MCUX_IMX_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
+#define MCUX_IMX_INPUT_ENABLE(x) ((x >> MCUX_IMX_INPUT_ENABLE_SHIFT) & 0x1)
+
+
+/*
+ * RT11xx has multiple types of register layouts defined for pin configuration
+ * registers. There are four types defined:
+ * pdrv_pull: registers lack a slew rate and pus field
+ * pue_pus: registers have a slew rate and ode field
+ * pue_pus_lpsr: in low power state retention domain, shifted ode field
+ * pue_pus_snvs: in SNVS domain, shifted ode field
+ */
+
+#define MCUX_IMX_PUS_PUE 0
+#define MCUX_IMX_PDRV_PULL 1
+#define MCUX_IMX_LPSR 2
+#define MCUX_IMX_SNVS 3
+
+/*
+ * Macro for MCUX_IMX_PULL_NOPULL, which needs to set field to 0x3 if two
+ * properties are false
+ */
+#define MCUX_IMX_NOPULL(node_id)								\
+	((0x2 & ((!DT_PROP(node_id, bias_pull_down) && !DT_PROP(node_id, bias_pull_up)) << 1)) |\
+	(0x1 & ((!DT_PROP(node_id, bias_pull_down) && !DT_PROP(node_id, bias_pull_up)) << 0)))	\
+
+#define Z_PINCTRL_MCUX_IMX_PDRV(node_id)							\
+	IF_ENABLED(DT_PROP(node_id, bias_pull_down),						\
+		(MCUX_IMX_PULL_PULLDOWN << MCUX_IMX_PULL_SHIFT) |)				\
+	IF_ENABLED(DT_PROP(node_id, bias_pull_up),						\
+		(MCUX_IMX_PULL_PULLUP << MCUX_IMX_PULL_SHIFT) |)				\
+	(MCUX_IMX_NOPULL(node_id) << MCUX_IMX_PULL_SHIFT) |					\
+	(DT_ENUM_IDX_OR(node_id, drive_strength, 0) << MCUX_IMX_PDRV_SHIFT) |			\
+	(DT_PROP(node_id, drive_open_drain) << MCUX_IMX_ODE_SHIFT) |				\
+	(DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT)
+
+#define Z_PINCTRL_MCUX_IMX_PUE_PUS(node_id)							\
+	(DT_PROP(node_id, bias_pull_up) << MCUX_IMX_PUS_SHIFT) |				\
+	((DT_PROP(node_id, bias_pull_up) || DT_PROP(node_id, bias_pull_down))			\
+		<< MCUX_IMX_PUE_SHIFT) |							\
+	(DT_ENUM_IDX_OR(node_id, drive_strength, 0) << MCUX_IMX_DSE_SHIFT) |			\
+	(DT_ENUM_IDX_OR(node_id, slew_rate, 0) << MCUX_IMX_SRE_SHIFT) |				\
+	(DT_PROP(node_id, drive_open_drain) << MCUX_IMX_ODE_SHIFT) |				\
+	(DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT)
+
+/* This struct must be present. It is used by the mcux gpio driver */
+struct pinctrl_soc_pinmux {
+	uint32_t mux_register; /* IOMUXC SW_PAD_MUX register */
+	uint32_t config_register; /* IOMUXC SW_PAD_CTL register */
+	uint32_t input_register; /* IOMUXC SELECT_INPUT DAISY register */
+	uint8_t mux_mode: 4; /* Mux value for SW_PAD_MUX register */
+	uint32_t input_daisy:4; /* Mux value for SELECT_INPUT_DAISY register */
+	uint8_t pue_mux: 1; /* Is pinmux reg pue type */
+	uint8_t pdrv_mux: 1; /* Is pinmux reg pdrv type */
+};
+
+struct pinctrl_soc_pin {
+	struct pinctrl_soc_pinmux pinmux;
+	uint32_t pin_ctrl_flags; /* value to write to IOMUXC_SW_PAD_CTL register */
+};
+
+typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
+
+/* This definition must be present. It is used by the mcux gpio driver */
+#define MCUX_IMX_PINMUX(node_id)						\
+	{									\
+	  .mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0),			\
+	  .config_register = DT_PROP_BY_IDX(node_id, pinmux, 4),		\
+	  .input_register = DT_PROP_BY_IDX(node_id, pinmux, 2),			\
+	  .mux_mode = DT_PROP_BY_IDX(node_id, pinmux, 1),			\
+	  .input_daisy = DT_PROP_BY_IDX(node_id, pinmux, 3),			\
+	  .pue_mux = DT_PROP(node_id, pin_pue),					\
+	  .pdrv_mux = DT_PROP(node_id, pin_pdrv),				\
+	}
+
+#define Z_PINCTRL_PINMUX(group_id, pin_prop, idx)				\
+	MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
+
+#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx)			\
+	{									\
+	  .pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx),			\
+IF_ENABLED(DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_pue),	\
+	  (.pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_PUE_PUS(group_id),))		\
+IF_ENABLED(DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_pdrv),	\
+	  (.pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_PDRV(group_id),))		\
+	},
+
+#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop)			\
+	{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop),		\
+		DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)};	\
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_RT118X_H_ */

soc/nxp/imxrt/imxrt118x/soc.c

@@ -0,0 +1,373 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <soc.h>
+#include <zephyr/linker/sections.h>
+#include <zephyr/linker/linker-defs.h>
+#if defined(CONFIG_SOC_MIMXRT1189_CM7)
+#include <zephyr/cache.h>
+#elif defined(CONFIG_IMXRT118X_CM33_XCACHE_PS)
+#include <fsl_cache.h>
+#endif
+#include <fsl_clock.h>
+#include <fsl_gpc.h>
+#include <fsl_pmu.h>
+#include <fsl_dcdc.h>
+#include <fsl_ele_base_api.h>
+#include <fsl_trdc.h>
+#include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
+#include <cmsis_core.h>
+
+/*
+ * Set ELE_STICK_FAILED_STS to 0 when ELE status check is not required,
+ * which is useful when debug reset, where the core has already get the
+ * TRDC ownership at first time and ELE is not able to release TRDC
+ * ownership again for the following TRDC ownership request.
+ */
+#define ELE_STICK_FAILED_STS 1
+
+#if ELE_STICK_FAILED_STS
+#define ELE_IS_FAILED(x) (x != kStatus_Success)
+#else
+#define ELE_IS_FAILED(x) false
+#endif
+
+#define ELE_TRDC_AON_ID    0x74
+#define ELE_TRDC_WAKEUP_ID 0x78
+#define ELE_CORE_CM33_ID   0x1
+#define ELE_CORE_CM7_ID    0x2
+
+#ifdef CONFIG_INIT_ARM_PLL
+static const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = {
+#if defined(CONFIG_SOC_MIMXRT1189_CM33) || defined(CONFIG_SOC_MIMXRT1189_CM7)
+	/* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */
+	.postDivider = kCLOCK_PllPostDiv2,
+	/* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */
+	.loopDivider = 132,
+#else
+	#error "Unknown SOC, no pll configuration defined"
+#endif
+};
+#endif
+
+const clock_sys_pll1_config_t sysPll1Config_BOARD_BootClockRUN = {
+	/* Enable Sys Pll1 divide-by-2 clock or not */
+	.pllDiv2En = 1,
+	/* Enable Sys Pll1 divide-by-5 clock or not */
+	.pllDiv5En = 1,
+	/* Spread spectrum parameter */
+	.ss = NULL,
+	/* Enable spread spectrum or not */
+	.ssEnable = false,
+};
+
+const clock_sys_pll2_config_t sysPll2Config_BOARD_BootClockRUN = {
+	/* Denominator of spread spectrum */
+	.mfd = 268435455,
+	/* Spread spectrum parameter */
+	.ss = NULL,
+	/* Enable spread spectrum or not */
+	.ssEnable = false,
+};
+
+/**
+ * @brief Initialize the system clock
+ */
+static ALWAYS_INLINE void clock_init(void)
+{
+	clock_root_config_t rootCfg = {0};
+
+	/* Init OSC RC 400M */
+	CLOCK_OSC_EnableOscRc400M();
+	CLOCK_OSC_GateOscRc400M(false);
+
+#if CONFIG_CPU_CORTEX_M7
+	/* Switch both core to OscRC400M first */
+	rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc400M;
+	rootCfg.div = 1;
+	CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
+#endif
+
+#if CONFIG_CPU_CORTEX_M33
+	rootCfg.mux = kCLOCK_M33_ClockRoot_MuxOscRc400M;
+	rootCfg.div = 2;
+	CLOCK_SetRootClock(kCLOCK_Root_M33, &rootCfg);
+#endif
+
+#if CONFIG_CPU_CORTEX_M7
+	DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_CORE0, kDCDC_1P0Target1P1V);
+	DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_CORE1, kDCDC_1P0Target1P1V);
+	/* FBB need to be enabled in OverDrive(OD) mode */
+	PMU_EnableFBB(ANADIG_PMU, true);
+#endif
+
+	/* Config CLK_1M */
+	CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz);
+
+	/* Init OSC RC 24M */
+	CLOCK_OSC_EnableOscRc24M(true);
+
+	/* Config OSC 24M */
+	ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) |
+	ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) |
+	ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0);
+
+	/* Wait for 24M OSC to be stable. */
+	while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK !=
+			(ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)) {
+	}
+
+#ifdef CONFIG_INIT_ARM_PLL
+	/* Init Arm Pll. */
+	CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
+#endif
+
+	/* Init Sys Pll1. */
+	CLOCK_InitSysPll1(&sysPll1Config_BOARD_BootClockRUN);
+
+	/* Init Sys Pll2. */
+	CLOCK_InitSysPll2(&sysPll2Config_BOARD_BootClockRUN);
+	/* Init System Pll2 pfd0. */
+	CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27);
+	/* Init System Pll2 pfd1. */
+	CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16);
+	/* Init System Pll2 pfd2. */
+	CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24);
+	/* Init System Pll2 pfd3. */
+	CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32);
+
+	/* Init Sys Pll3. */
+	CLOCK_InitSysPll3();
+	/* Init System Pll3 pfd0. */
+	CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 22);
+	/* Init System Pll3 pfd1. */
+	CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 33);
+	/* Init System Pll3 pfd2. */
+	CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 22);
+	/* Init System Pll3 pfd3. */
+	CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 18);
+
+	/* Bypass Audio Pll. */
+	CLOCK_SetPllBypass(kCLOCK_PllAudio, true);
+	/* DeInit Audio Pll. */
+	CLOCK_DeinitAudioPll();
+
+#if defined(CONFIG_SOC_MIMXRT1189_CM7)
+	/* Module clock root configurations. */
+	/* Configure M7 using ARM_PLL_CLK */
+	rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut;
+	rootCfg.div = 1;
+	CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
+#endif
+
+#if defined(CONFIG_SOC_MIMXRT1189_CM33)
+	/* Configure M33 using SYS_PLL3_CLK */
+	rootCfg.mux = kCLOCK_M33_ClockRoot_MuxSysPll3Out;
+	rootCfg.div = 2;
+	CLOCK_SetRootClock(kCLOCK_Root_M33, &rootCfg);
+#endif
+
+	/* Configure BUS_AON using SYS_PLL2_CLK */
+	rootCfg.mux = kCLOCK_BUS_AON_ClockRoot_MuxSysPll2Out;
+	rootCfg.div = 4;
+	CLOCK_SetRootClock(kCLOCK_Root_Bus_Aon, &rootCfg);
+
+	/* Configure BUS_WAKEUP using SYS_PLL2_CLK */
+	rootCfg.mux = kCLOCK_BUS_WAKEUP_ClockRoot_MuxSysPll2Out;
+	rootCfg.div = 4;
+	CLOCK_SetRootClock(kCLOCK_Root_Bus_Wakeup, &rootCfg);
+
+	/* Configure WAKEUP_AXI using SYS_PLL3_CLK */
+	rootCfg.mux = kCLOCK_WAKEUP_AXI_ClockRoot_MuxSysPll3Out;
+	rootCfg.div = 2;
+	CLOCK_SetRootClock(kCLOCK_Root_Wakeup_Axi, &rootCfg);
+
+	/* Configure SWO_TRACE using SYS_PLL3_DIV2_CLK */
+	rootCfg.mux = kCLOCK_SWO_TRACE_ClockRoot_MuxSysPll3Div2;
+	rootCfg.div = 3;
+	CLOCK_SetRootClock(kCLOCK_Root_Swo_Trace, &rootCfg);
+
+#if CONFIG_CPU_CORTEX_M33
+	/* Configure M33_SYSTICK using OSC_24M */
+	rootCfg.mux = kCLOCK_M33_SYSTICK_ClockRoot_MuxOsc24MOut;
+	rootCfg.div = 240;
+	CLOCK_SetRootClock(kCLOCK_Root_M33_Systick, &rootCfg);
+#endif
+
+#if CONFIG_CPU_CORTEX_M7
+	/* Configure M7_SYSTICK using OSC_24M */
+	rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOsc24MOut;
+	rootCfg.div = 240;
+	CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
+#endif
+
+#if defined(CONFIG_UART_MCUX_LPUART) && \
+	(DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart1), okay) \
+	|| DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart2), okay))
+	/* Configure LPUART0102 using SYS_PLL3_DIV2_CLK */
+	rootCfg.mux = kCLOCK_LPUART0102_ClockRoot_MuxSysPll3Div2;
+	rootCfg.div = 10;
+#endif
+
+#if defined(CONFIG_I2C_MCUX_LPI2C) && \
+	(DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c1), okay) \
+	|| DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c2), okay))
+	/* Configure LPI2C0102 using SYS_PLL3_DIV2_CLK */
+	rootCfg.mux = kCLOCK_LPI2C0102_ClockRoot_MuxSysPll3Div2;
+	rootCfg.div = 4;
+	CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0102, &rootCfg);
+#endif
+
+#if defined(CONFIG_SPI_MCUX_LPSPI) && \
+	(DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi1), okay) \
+	|| DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi2), okay))
+	/* Configure LPSPI0102 using SYS_PLL3_PFD1_CLK */
+	rootCfg.mux = kCLOCK_LPSPI0102_ClockRoot_MuxSysPll3Pfd1;
+	rootCfg.div = 2;
+	CLOCK_SetRootClock(kCLOCK_Root_Lpspi0102, &rootCfg);
+#endif
+
+	/* Keep core clock ungated during WFI */
+	CCM->LPCG[1].LPM0 = 0x33333333;
+	CCM->LPCG[1].LPM1 = 0x33333333;
+	/* Keep the system clock running so SYSTICK can wake up
+	 * the system from wfi.
+	 */
+	GPC_CM_SetNextCpuMode(0, kGPC_RunMode);
+	GPC_CM_SetNextCpuMode(1, kGPC_RunMode);
+	GPC_CM_EnableCpuSleepHold(0, false);
+	GPC_CM_EnableCpuSleepHold(1, false);
+
+#if !defined(CONFIG_PM)
+	/* Enable the AHB clock while the CM7 is sleeping to allow debug access
+	 * to TCM
+	 */
+	BLK_CTRL_S_AONMIX->M7_CFG |= BLK_CTRL_S_AONMIX_M7_CFG_TCM_SIZE_MASK;
+#endif
+}
+
+/**
+ * @brief Initialize the system clock
+ */
+static ALWAYS_INLINE void trdc_enable_all_access(void)
+{
+	status_t sts;
+	uint8_t i, j;
+
+    /* Get ELE FW status */
+	do {
+		uint32_t ele_fw_sts;
+
+		sts = ELE_BaseAPI_GetFwStatus(MU_RT_S3MUA, &ele_fw_sts);
+	} while (sts != kStatus_Success);
+
+	do {
+#if defined(CONFIG_SOC_MIMXRT1189_CM33)
+		/* Release TRDC A to CM33 core */
+		sts = ELE_BaseAPI_ReleaseRDC(MU_RT_S3MUA, ELE_TRDC_AON_ID, ELE_CORE_CM33_ID);
+#elif defined(CONFIG_SOC_MIMXRT1189_CM7)
+		/* Release TRDC A to CM7 core */
+		sts = ELE_BaseAPI_ReleaseRDC(MU_RT_S3MUA, ELE_TRDC_AON_ID, ELE_CORE_CM7_ID);
+#endif
+	} while (ELE_IS_FAILED(sts));
+
+	/* Release TRDC W to CM33 core */
+	do {
+#if defined(CONFIG_SOC_MIMXRT1189_CM33)
+		/* Release TRDC A to CM33 core */
+		sts = ELE_BaseAPI_ReleaseRDC(MU_RT_S3MUA, ELE_TRDC_WAKEUP_ID, ELE_CORE_CM33_ID);
+#elif defined(CONFIG_SOC_MIMXRT1189_CM7)
+		/* Release TRDC A to CM7 core */
+		sts = ELE_BaseAPI_ReleaseRDC(MU_RT_S3MUA, ELE_TRDC_WAKEUP_ID, ELE_CORE_CM7_ID);
+#endif
+	} while (ELE_IS_FAILED(sts));
+
+	/* Enable all access modes for MBC and MRC of TRDCA and TRDCW */
+	trdc_hardware_config_t hwConfig;
+	trdc_memory_access_control_config_t memAccessConfig;
+
+	(void)memset(&memAccessConfig, 0, sizeof(memAccessConfig));
+	memAccessConfig.nonsecureUsrX  = 1U;
+	memAccessConfig.nonsecureUsrW  = 1U;
+	memAccessConfig.nonsecureUsrR  = 1U;
+	memAccessConfig.nonsecurePrivX = 1U;
+	memAccessConfig.nonsecurePrivW = 1U;
+	memAccessConfig.nonsecurePrivR = 1U;
+	memAccessConfig.secureUsrX     = 1U;
+	memAccessConfig.secureUsrW     = 1U;
+	memAccessConfig.secureUsrR     = 1U;
+	memAccessConfig.securePrivX    = 1U;
+	memAccessConfig.securePrivW    = 1U;
+	memAccessConfig.securePrivR    = 1U;
+
+	TRDC_GetHardwareConfig(TRDC1, &hwConfig);
+	for (i = 0U; i < hwConfig.mrcNumber; i++) {
+		for (j = 0U; j < 8; j++) {
+			TRDC_MrcSetMemoryAccessConfig(TRDC1, &memAccessConfig, i, j);
+		}
+	}
+
+	for (i = 0U; i < hwConfig.mbcNumber; i++) {
+		for (j = 0U; j < 8; j++) {
+			TRDC_MbcSetMemoryAccessConfig(TRDC1, &memAccessConfig, i, j);
+		}
+	}
+
+	TRDC_GetHardwareConfig(TRDC2, &hwConfig);
+	for (i = 0U; i < hwConfig.mrcNumber; i++) {
+		for (j = 0U; j < 8; j++) {
+			TRDC_MrcSetMemoryAccessConfig(TRDC2, &memAccessConfig, i, j);
+		}
+	}
+
+	for (i = 0U; i < hwConfig.mbcNumber; i++) {
+		for (j = 0U; j < 8; j++) {
+			TRDC_MbcSetMemoryAccessConfig(TRDC2, &memAccessConfig, i, j);
+		}
+	}
+}
+
+/**
+ *
+ * @brief Perform basic hardware initialization
+ *
+ * Initialize the interrupt controller device drivers.
+ * Also initialize the timer device driver, if required.
+ * If dual core operation is enabled, the second core image will be loaded to RAM
+ *
+ * @return 0
+ */
+
+static int imxrt_init(void)
+{
+	/* Initialize system clock */
+	clock_init();
+	/* Get trdc and enable all access modes for MBC and MRC of TRDCA and TRDCW */
+	trdc_enable_all_access();
+
+	/* Enable data cache */
+#if defined(CONFIG_IMXRT118X_CM33_XCACHE_PS)
+	XCACHE_EnableCache(XCACHE_PS);
+#elif defined(CONFIG_SOC_MIMXRT1189_CM7)
+	sys_cache_data_enable();
+#endif
+	__ISB();
+	__DSB();
+
+	return 0;
+}
+
+#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
+void z_arm_platform_init(void)
+{
+	SystemInit();
+}
+#endif
+
+SYS_INIT(imxrt_init, PRE_KERNEL_1, 0);

soc/nxp/imxrt/imxrt118x/soc.h

@@ -0,0 +1,29 @@
+/*
+ * Copyright 2024, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SOC__H_
+#define _SOC__H_
+
+#include <zephyr/sys/util.h>
+
+#ifndef _ASMLANGUAGE
+
+#include <fsl_common.h>
+
+/* Add include for DTS generated information */
+#include <zephyr/devicetree.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _SOC__H_ */

soc/nxp/imxrt/soc.yml

@@ -23,6 +23,12 @@ family:
       cpuclusters:
       - name: cm7
       - name: cm4
+  - name: imxrt118x
+    socs:
+    - name: mimxrt1189
+      cpuclusters:
+      - name: cm33
+      - name: cm7
   - name: imxrt5xx
     socs:
     - name: mimxrt595s