interrupt_controller: added support for the SiFive Freedom E310 PLIC driver
The SiFive Freedom E310 Platform Level Interrupt Controller (PLIC) follows the riscv PLIC specification as defined in the riscv privilege architecture specification. It provides implementation for the riscv PLIC APIs as required by the riscv-privilege SOC Family for SOCs providing support for the RISCV_HAS_PLIC config. Change-Id: I95d02edb53deeccd91e490776e8e1dbfb82d235f Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
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Jean-Paul Etienne
Anas Nashif
parent
f2c96e8fff
commit
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3 changed files with 236 additions and 0 deletions
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@ -124,6 +124,15 @@ config ARCV2_INTERRUPT_UNIT
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building a processor, you can configure the processor to include an
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interrupt unit. The ARCv2 interrupt unit is highly programmable.
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config PLIC_FE310
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bool "SiFive Freedom E310 Platform Level Interrupt Controller (PLIC)"
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default y
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depends on SOC_RISCV32_FE310
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select RISCV_HAS_PLIC
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help
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SiFive Freedom E310 Platform Level Interrupt Controller provides support
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for external interrupt lines defined by the FE310 SOC;
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source "drivers/interrupt_controller/Kconfig.stm32"
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endmenu
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@ -8,3 +8,5 @@ obj-$(CONFIG_LOAPIC_SPURIOUS_VECTOR) += loapic_spurious.o
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obj-$(CONFIG_ARCV2_INTERRUPT_UNIT) += arcv2_irq_unit.o
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obj-$(CONFIG_SOC_FAMILY_STM32) += exti_stm32.o
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obj-$(CONFIG_PLIC_FE310) += plic_fe310.o
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225
drivers/interrupt_controller/plic_fe310.c
Normal file
225
drivers/interrupt_controller/plic_fe310.c
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@ -0,0 +1,225 @@
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/*
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* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief Platform Level Interrupt Controller (PLIC) driver
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* for the SiFive Freedom E310 processor
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*/
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <init.h>
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#include <soc.h>
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#include <sw_isr_table.h>
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#define PLIC_FE310_IRQS (CONFIG_NUM_IRQS - RISCV_MAX_GENERIC_IRQ)
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#define PLIC_FE310_EN_SIZE ((PLIC_FE310_IRQS >> 5) + 1)
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struct plic_fe310_regs_t {
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uint32_t threshold_prio;
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uint32_t claim_complete;
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};
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static int save_irq;
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/**
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*
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* @brief Enable a riscv PLIC-specific interrupt line
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*
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* This routine enables a RISCV PLIC-specific interrupt line.
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* riscv_plic_irq_enable is called by SOC_FAMILY_RISCV_PRIVILEGE
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* _arch_irq_enable function to enable external interrupts for
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* IRQS > RISCV_MAX_GENERIC_IRQ, whenever CONFIG_RISCV_HAS_PLIC
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* variable is set.
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* @param irq IRQ number to enable
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*
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* @return N/A
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*/
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void riscv_plic_irq_enable(uint32_t irq)
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{
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uint32_t key;
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uint32_t fe310_irq = irq - RISCV_MAX_GENERIC_IRQ;
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volatile uint32_t *en =
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(volatile uint32_t *)FE310_PLIC_IRQ_EN_BASE_ADDR;
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key = irq_lock();
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en += (fe310_irq >> 5);
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*en |= (1 << (fe310_irq & 31));
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irq_unlock(key);
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}
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/**
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*
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* @brief Disable a riscv PLIC-specific interrupt line
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*
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* This routine disables a RISCV PLIC-specific interrupt line.
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* riscv_plic_irq_disable is called by SOC_FAMILY_RISCV_PRIVILEGE
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* _arch_irq_disable function to disable external interrupts, for
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* IRQS > RISCV_MAX_GENERIC_IRQ, whenever CONFIG_RISCV_HAS_PLIC
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* variable is set.
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* @param irq IRQ number to disable
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*
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* @return N/A
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*/
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void riscv_plic_irq_disable(uint32_t irq)
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{
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uint32_t key;
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uint32_t fe310_irq = irq - RISCV_MAX_GENERIC_IRQ;
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volatile uint32_t *en =
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(volatile uint32_t *)FE310_PLIC_IRQ_EN_BASE_ADDR;
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key = irq_lock();
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en += (fe310_irq >> 5);
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*en &= ~(1 << (fe310_irq & 31));
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irq_unlock(key);
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}
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/**
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*
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* @brief Check if a riscv PLIC-specific interrupt line is enabled
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*
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* This routine checks if a RISCV PLIC-specific interrupt line is enabled.
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* @param irq IRQ number to check
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*
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* @return 1 or 0
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*/
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int riscv_plic_irq_is_enabled(uint32_t irq)
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{
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volatile uint32_t *en =
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(volatile uint32_t *)FE310_PLIC_IRQ_EN_BASE_ADDR;
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uint32_t fe310_irq = irq - RISCV_MAX_GENERIC_IRQ;
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en += (fe310_irq >> 5);
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return !!(*en & (1 << (fe310_irq & 31)));
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}
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/**
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*
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* @brief Set priority of a riscv PLIC-specific interrupt line
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*
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* This routine set the priority of a RISCV PLIC-specific interrupt line.
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* riscv_plic_irq_set_prio is called by riscv32 _ARCH_IRQ_CONNECT to set
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* the priority of an interrupt whenever CONFIG_RISCV_HAS_PLIC variable is set.
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* @param irq IRQ number for which to set priority
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*
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* @return N/A
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*/
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void riscv_plic_set_priority(uint32_t irq, uint32_t priority)
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{
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volatile uint32_t *prio =
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(volatile uint32_t *)FE310_PLIC_PRIO_BASE_ADDR;
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/* Can set priority only for PLIC-specific interrupt line */
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if (irq <= RISCV_MAX_GENERIC_IRQ)
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return;
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if (priority > FE310_PLIC_MAX_PRIORITY)
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priority = FE310_PLIC_MAX_PRIORITY;
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prio += (irq - RISCV_MAX_GENERIC_IRQ);
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*prio = priority;
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}
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/**
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*
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* @brief Get riscv PLIC-specific interrupt line causing an interrupt
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*
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* This routine returns the RISCV PLIC-specific interrupt line causing an
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* interrupt.
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* @param irq IRQ number for which to set priority
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*
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* @return N/A
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*/
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int riscv_plic_get_irq(void)
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{
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return save_irq;
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}
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static void plic_fe310_irq_handler(void *arg)
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{
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volatile struct plic_fe310_regs_t *regs =
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(volatile struct plic_fe310_regs_t *)FE310_PLIC_REG_BASE_ADDR;
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uint32_t irq;
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struct _isr_table_entry *ite;
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/* Get the IRQ number generating the interrupt */
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irq = regs->claim_complete;
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/*
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* Save IRQ in save_irq. To be used, if need be, by
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* subsequent handlers registered in the _sw_isr_table table,
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* as IRQ number held by the claim_complete register is
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* cleared upon read.
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*/
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save_irq = irq;
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/*
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* If the IRQ is out of range, call _irq_spurious.
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* A call to _irq_spurious will not return.
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*/
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if (irq == 0 || irq >= PLIC_FE310_IRQS)
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_irq_spurious(NULL);
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irq += RISCV_MAX_GENERIC_IRQ;
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/* Call the corresponding IRQ handler in _sw_isr_table */
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ite = (struct _isr_table_entry *)&_sw_isr_table[irq];
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ite->isr(ite->arg);
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/*
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* Write to claim_complete register to indicate to
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* PLIC controller that the IRQ has been handled.
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*/
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regs->claim_complete = save_irq;
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}
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/**
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*
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* @brief Initialize the SiFive FE310 Platform Level Interrupt Controller
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* @return N/A
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*/
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static int plic_fe310_init(struct device *dev)
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{
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ARG_UNUSED(dev);
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volatile uint32_t *en =
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(volatile uint32_t *)FE310_PLIC_IRQ_EN_BASE_ADDR;
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volatile uint32_t *prio =
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(volatile uint32_t *)FE310_PLIC_PRIO_BASE_ADDR;
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volatile struct plic_fe310_regs_t *regs =
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(volatile struct plic_fe310_regs_t *)FE310_PLIC_REG_BASE_ADDR;
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int i;
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/* Ensure that all interrupts are disabled initially */
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for (i = 0; i < PLIC_FE310_EN_SIZE; i++) {
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*en = 0;
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en++;
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}
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/* Set priority of each interrupt line to 0 initially */
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for (i = 0; i < PLIC_FE310_IRQS; i++) {
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*prio = 0;
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prio++;
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}
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/* Set threshold priority to 0 */
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regs->threshold_prio = 0;
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/* Setup IRQ handler for PLIC driver */
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IRQ_CONNECT(RISCV_MACHINE_EXT_IRQ,
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0,
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plic_fe310_irq_handler,
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NULL,
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0);
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/* Enable IRQ for PLIC driver */
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irq_enable(RISCV_MACHINE_EXT_IRQ);
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return 0;
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}
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SYS_INIT(plic_fe310_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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