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riscv_machine_timer: Enable to use divided clock for the machine timer

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GD32V SoC uses divided clock from core-clock for machine timer clock.
Add config of clock divide factor to support GD32V.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This commit is contained in:
TOKITA Hiroshi 2020-03-08 23:21:21 +09:00 • committed by Carles Cufí
commit d79d4f0bea
4 changed files with 83 additions and 4 deletions
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22
include/dt-bindings/timer/riscv-machine-timer.h Normal file
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/*
* Copyright (c) 2021, TOKITA Hiroshi <tokita.hiroshi@gmail.com>
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_TIMER_RISCV_MACHINE_TIMER_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_TIMER_RISCV_MACHINE_TIMER_H_
/* Clock divider values */
#define RISCV_MACHINE_TIMER_DIVIDER_1 0
#define RISCV_MACHINE_TIMER_DIVIDER_2 1
#define RISCV_MACHINE_TIMER_DIVIDER_4 2
#define RISCV_MACHINE_TIMER_DIVIDER_8 3
#define RISCV_MACHINE_TIMER_DIVIDER_16 4
#define RISCV_MACHINE_TIMER_DIVIDER_32 5
#define RISCV_MACHINE_TIMER_DIVIDER_64 6
#define RISCV_MACHINE_TIMER_DIVIDER_128 7
#define RISCV_MACHINE_TIMER_DIVIDER_256 8
#define RISCV_MACHINE_TIMER_DIVIDER_512 9
#define RISCV_MACHINE_TIMER_DIVIDER_1024 10
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_TIMER_RISCV_MACHINE_TIMER_H_ */