diff --git a/arch/x86/soc/atom/Kconfig.defconfig b/arch/x86/soc/atom/Kconfig.defconfig
index 2702fe48a18..e6b49fbf313 100644
--- a/arch/x86/soc/atom/Kconfig.defconfig
+++ b/arch/x86/soc/atom/Kconfig.defconfig
@@ -11,11 +11,13 @@ if SOC_ATOM
 config SOC
 	default atom
 
+if !HAS_DTS
 config PHYS_LOAD_ADDR
 	default 0x00100000
 
 config PHYS_RAM_ADDR
 	default 0x00400000
+endif
 
 config RAM_SIZE
 	default 128 if XIP
@@ -41,12 +43,16 @@ config UART_NS16550_PORT_0
 
 if UART_NS16550_PORT_0
 
+if !HAS_DTS
 config UART_NS16550_PORT_0_NAME
 	default "UART_0"
+endif
 config UART_NS16550_PORT_0_IRQ_PRI
 	default 3
+if !HAS_DTS
 config UART_NS16550_PORT_0_BAUD_RATE
 	default 115200
+endif
 config UART_NS16550_PORT_0_OPTIONS
 	default 0
 
@@ -57,12 +63,16 @@ config UART_NS16550_PORT_1
 
 if UART_NS16550_PORT_1
 
+if !HAS_DTS
 config UART_NS16550_PORT_1_NAME
 	default "UART_1"
+endif
 config UART_NS16550_PORT_1_IRQ_PRI
 	default 3
+if !HAS_DTS
 config UART_NS16550_PORT_1_BAUD_RATE
 	default 115200
+endif
 config UART_NS16550_PORT_1_OPTIONS
 	default 0
 
@@ -72,6 +82,7 @@ endif # UART_NS16550
 
 if BT_UART
 
+if !HAS_DTS
 config BT_UART_ON_DEV_NAME
 	default "UART_1"
 
@@ -86,5 +97,6 @@ endif
 
 config BT_MONITOR_ON_DEV_NAME
 	default "UART_1" if BT_DEBUG_MONITOR
+endif
 
 endif
diff --git a/arch/x86/soc/atom/linker.ld b/arch/x86/soc/atom/linker.ld
index ab0f5d97ae6..8ed93c1ecad 100644
--- a/arch/x86/soc/atom/linker.ld
+++ b/arch/x86/soc/atom/linker.ld
@@ -12,7 +12,7 @@
  */
 
 #include <autoconf.h>
-
+#include <generated_dts_board.h>
 /* physical address where the kernel is loaded */
 #define PHYS_LOAD_ADDR CONFIG_PHYS_LOAD_ADDR
 
diff --git a/dts/x86/atom.dtsi b/dts/x86/atom.dtsi
new file mode 100644
index 00000000000..26160d4053f
--- /dev/null
+++ b/dts/x86/atom.dtsi
@@ -0,0 +1,52 @@
+#include "skeleton.dtsi"
+
+#define __SIZE_K(x) (x * 1024)
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "atom";
+			reg = <0>;
+		};
+
+	};
+
+	flash0: flash@00100000{
+		reg = <0x00100000 DT_FLASH_SIZE>;
+	};
+
+	sram0: memory@00400000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0x00400000 DT_SRAM_SIZE>;
+	};
+
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+
+		uart0: uart@f0008000 {
+			compatible = "ns16550";
+			reg = <0xf0008000 0x400>;
+			label = "UART_0";
+
+			status = "disabled";
+		};
+
+		uart1: uart@f0009000 {
+			compatible = "ns16550";
+			reg = <0xf0009000 0x400>;
+			label = "UART_1";
+
+			status = "disabled";
+		};
+	};
+};