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boards: dts: stm32: add mdio and phy node

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add mdio and phy node to every stm32board that
supports ethernet.
Also set the phy-handle for every ethernet mac.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
This commit is contained in:
Fin Maaß 2025-03-26 07:46:37 +01:00 • committed by Benjamin Cabé
commit d74d0f7ac7
29 changed files with 189 additions and 60 deletions
Download patch file Download diff file Expand all files Collapse all files

4
boards/arduino/opta/arduino_opta_stm32h747xx_m7.dts
View file

@ -108,6 +108,7 @@ zephyr_udc0: &usbotg_fs {
>;
pinctrl-names = "default";
phy-connection-type = "rmii";
phy-handle = <&eth_phy>;
status = "okay";
};
@ -116,9 +117,8 @@ zephyr_udc0: &usbotg_fs {
pinctrl-names = "default";
status = "okay";
ethernet-phy@0 {
eth_phy: ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0x00>;
status = "okay";
};
};

4
boards/arduino/portenta_h7/arduino_portenta_h7-common.dtsi
View file

@ -223,6 +223,7 @@
&eth_txd0_pg13 >;
pinctrl-names = "default";
phy-connection-type = "rmii";
phy-handle = <&eth_phy>;
status = "okay";
};
@ -231,10 +232,9 @@
pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
pinctrl-names = "default";
ethernet-phy@0 {
eth_phy: ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0x00>;
status = "okay";
};
};

16
boards/olimex/stm32_e407/olimex_stm32_e407.dts
View file

@ -116,11 +116,9 @@ zephyr_udc0: &usbotg_hs {
&mac {
status = "okay";
pinctrl-0 = <&eth_mdc_pc1
&eth_rxd0_pc4
pinctrl-0 = <&eth_rxd0_pc4
&eth_rxd1_pc5
&eth_ref_clk_pa1
&eth_mdio_pa2
&eth_col_pa3
&eth_crs_dv_pa7
&eth_tx_en_pg11
@ -128,4 +126,16 @@ zephyr_udc0: &usbotg_hs {
&eth_txd1_pg14>;
pinctrl-names = "default";
phy-connection-type = "rmii";
phy-handle = <&eth_phy>;
};
&mdio {
status = "okay";
pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
pinctrl-names = "default";
eth_phy: ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0x00>;
};
};

16
boards/st/nucleo_f207zg/nucleo_f207zg.dts
View file

@ -179,17 +179,27 @@ zephyr_udc0: &usbotg_fs {
&mac {
status = "okay";
pinctrl-0 = <&eth_mdc_pc1
&eth_rxd0_pc4
pinctrl-0 = <&eth_rxd0_pc4
&eth_rxd1_pc5
&eth_ref_clk_pa1
&eth_mdio_pa2
&eth_crs_dv_pa7
&eth_tx_en_pg11
&eth_txd0_pg13
&eth_txd1_pb13>;
pinctrl-names = "default";
phy-connection-type = "rmii";
phy-handle = <&phy>;
};
&mdio {
status = "okay";
pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
pinctrl-names = "default";
phy: ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0x00>;
};
};
&flash0 {

16
boards/st/nucleo_f429zi/nucleo_f429zi.dts
View file

@ -176,17 +176,27 @@ zephyr_udc0: &usbotg_fs {
&mac {
status = "okay";
pinctrl-0 = <&eth_mdc_pc1
&eth_rxd0_pc4
pinctrl-0 = <&eth_rxd0_pc4
&eth_rxd1_pc5
&eth_ref_clk_pa1
&eth_mdio_pa2
&eth_crs_dv_pa7
&eth_tx_en_pg11
&eth_txd0_pg13
&eth_txd1_pb13>;
pinctrl-names = "default";
phy-connection-type = "rmii";
phy-handle = <&eth_phy>;
};
&mdio {
status = "okay";
pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
pinctrl-names = "default";
eth_phy: ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0x00>;
};
};
&flash0 {

16
boards/st/nucleo_f439zi/nucleo_f439zi.dts
View file

@ -180,17 +180,27 @@ zephyr_udc0: &usbotg_fs {
&mac {
status = "okay";
pinctrl-0 = <&eth_mdc_pc1
&eth_rxd0_pc4
pinctrl-0 = <&eth_rxd0_pc4
&eth_rxd1_pc5
&eth_ref_clk_pa1
&eth_mdio_pa2
&eth_crs_dv_pa7
&eth_tx_en_pg11
&eth_txd0_pg13
&eth_txd1_pb13>;
pinctrl-names = "default";
phy-connection-type = "rmii";
phy-handle = <&eth_phy>;
};
&mdio {
status = "okay";
pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
pinctrl-names = "default";
eth_phy: ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0x00>;
};
};
&flash0 {

16
boards/st/nucleo_f746zg/nucleo_f746zg.dts
View file

@ -197,17 +197,27 @@ zephyr_udc0: &usbotg_fs {
&mac {
status = "okay";
pinctrl-0 = <&eth_mdc_pc1
&eth_rxd0_pc4
pinctrl-0 = <&eth_rxd0_pc4
&eth_rxd1_pc5
&eth_ref_clk_pa1
&eth_mdio_pa2
&eth_crs_dv_pa7
&eth_tx_en_pg11
&eth_txd0_pg13
&eth_txd1_pb13>;
pinctrl-names = "default";
phy-connection-type = "rmii";
phy-handle = <&eth_phy>;
};
&mdio {
status = "okay";
pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
pinctrl-names = "default";
eth_phy: ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0x00>;
};
};
&backup_sram {

17
boards/st/nucleo_f756zg/nucleo_f756zg.dts
View file

@ -141,19 +141,30 @@ zephyr_udc0: &usbotg_fs {
&mac {
status = "okay";
pinctrl-0 = <&eth_mdc_pc1
&eth_rxd0_pc4
pinctrl-0 = <&eth_rxd0_pc4
&eth_rxd1_pc5
&eth_ref_clk_pa1
&eth_mdio_pa2
&eth_crs_dv_pa7
&eth_tx_en_pg11
&eth_txd0_pg13
&eth_txd1_pb13>;
pinctrl-names = "default";
phy-connection-type = "rmii";
phy-handle = <&eth_phy>;
};
&mdio {
status = "okay";
pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
pinctrl-names = "default";
eth_phy: ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0x00>;
};
};
&flash0 {
partitions {
compatible = "fixed-partitions";

16
boards/st/nucleo_f767zi/nucleo_f767zi.dts
View file

@ -188,17 +188,27 @@ zephyr_udc0: &usbotg_fs {
&mac {
status = "okay";
pinctrl-0 = <&eth_mdc_pc1
&eth_rxd0_pc4
pinctrl-0 = <&eth_rxd0_pc4
&eth_rxd1_pc5
&eth_ref_clk_pa1
&eth_mdio_pa2
&eth_crs_dv_pa7
&eth_tx_en_pg11
&eth_txd0_pg13
&eth_txd1_pb13>;
pinctrl-names = "default";
phy-connection-type = "rmii";
phy-handle = <&eth_phy>;
};
&mdio {
status = "okay";
pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
pinctrl-names = "default";
eth_phy: ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0x00>;
};
};
&flash0 {

4
boards/st/nucleo_h563zi/nucleo_h563zi.dts
View file

@ -50,6 +50,7 @@
&eth_txd1_pb15>;
pinctrl-names = "default";
phy-connection-type = "rmii";
phy-handle = <&eth_phy>;
};
&mdio {
@ -57,9 +58,8 @@
pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
pinctrl-names = "default";
ethernet-phy@0 {
eth_phy: ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0x00>;
status = "okay";
};
};

4
boards/st/nucleo_h723zg/nucleo_h723zg.dts
View file

@ -179,6 +179,7 @@
&eth_txd1_pb13>;
pinctrl-names = "default";
phy-connection-type = "rmii";
phy-handle = <&eth_phy>;
};
&mdio {
@ -186,10 +187,9 @@
pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
pinctrl-names = "default";
phy: ethernet-phy@0 {
eth_phy: ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0>;
status = "okay";
};
};

4
boards/st/nucleo_h743zi/nucleo_h743zi.dts
View file

@ -204,6 +204,7 @@ zephyr_udc0: &usbotg_fs {
&eth_txd1_pb13>;
pinctrl-names = "default";
phy-connection-type = "rmii";
phy-handle = <&eth_phy>;
};
&mdio {
@ -211,10 +212,9 @@ zephyr_udc0: &usbotg_fs {
pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
pinctrl-names = "default";
ethernet-phy@0 {
eth_phy: ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0x00>;
status = "okay";
};
};

4
boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts
View file

@ -116,6 +116,7 @@
&eth_txd1_pb13>;
pinctrl-names = "default";
phy-connection-type = "rmii";
phy-handle = <&eth_phy>;
};
&mdio {
@ -123,10 +124,9 @@
pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
pinctrl-names = "default";
ethernet-phy@0 {
eth_phy: ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0x00>;
status = "okay";
};
};

4
boards/st/nucleo_h753zi/nucleo_h753zi.dts
View file

@ -183,6 +183,7 @@ zephyr_udc0: &usbotg_fs {
&eth_txd1_pb13>;
pinctrl-names = "default";
phy-connection-type = "rmii";
phy-handle = <&eth_phy>;
};
&mdio {
@ -190,10 +191,9 @@ zephyr_udc0: &usbotg_fs {
pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
pinctrl-names = "default";
ethernet-phy@0 {
eth_phy: ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0x00>;
status = "okay";
};
};

4
boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7.dts
View file

@ -134,6 +134,7 @@
&eth_txd1_pb13>;
pinctrl-names = "default";
phy-connection-type = "rmii";
phy-handle = <&eth_phy>;
};
&mdio {
@ -141,10 +142,9 @@
pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
pinctrl-names = "default";
ethernet-phy@0 {
eth_phy: ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0x00>;
status = "okay";
};
};

4
boards/st/nucleo_n657x0_q/nucleo_n657x0_q_common.dtsi
View file

@ -188,6 +188,7 @@
&eth1_rmii_txd1_pf13>;
pinctrl-names = "default";
phy-connection-type = "rmii";
phy-handle = <&eth_phy>;
};
&mdio {
@ -195,10 +196,9 @@
pinctrl-0 = <&eth1_mdio_pf4 &eth1_mdc_pg11>;
pinctrl-names = "default";
ethernet-phy@0 {
eth_phy: ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0x0>;
status = "okay";
};
};

16
boards/st/stm32f746g_disco/stm32f746g_disco.dts
View file

@ -177,17 +177,27 @@ zephyr_udc0: &usbotg_fs {
&mac {
status = "okay";
pinctrl-0 = <&eth_mdc_pc1
&eth_rxd0_pc4
pinctrl-0 = <&eth_rxd0_pc4
&eth_rxd1_pc5
&eth_ref_clk_pa1
&eth_mdio_pa2
&eth_crs_dv_pa7
&eth_tx_en_pg11
&eth_txd0_pg13
&eth_txd1_pg14>;
pinctrl-names = "default";
phy-connection-type = "rmii";
phy-handle = <&eth_phy>;
};
&mdio {
status = "okay";
pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
pinctrl-names = "default";
eth_phy: ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0x00>;
};
};
&quadspi {

16
boards/st/stm32f7508_dk/stm32f7508_dk.dts
View file

@ -164,17 +164,27 @@ zephyr_udc0: &usbotg_fs {
&mac {
status = "okay";
pinctrl-0 = <&eth_mdc_pc1
&eth_rxd0_pc4
pinctrl-0 = <&eth_rxd0_pc4
&eth_rxd1_pc5
&eth_ref_clk_pa1
&eth_mdio_pa2
&eth_crs_dv_pa7
&eth_tx_en_pg11
&eth_txd0_pg13
&eth_txd1_pg14>;
pinctrl-names = "default";
phy-connection-type = "rmii";
phy-handle = <&eth_phy>;
};
&mdio {
status = "okay";
pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
pinctrl-names = "default";
eth_phy: ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0x00>;
};
};
&quadspi {

16
boards/st/stm32f769i_disco/stm32f769i_disco.dts
View file

@ -151,17 +151,27 @@ arduino_serial: &usart6 {};
&mac {
status = "okay";
pinctrl-0 = <&eth_mdc_pc1
&eth_rxd0_pc4
pinctrl-0 = <&eth_rxd0_pc4
&eth_rxd1_pc5
&eth_ref_clk_pa1
&eth_mdio_pa2
&eth_crs_dv_pa7
&eth_tx_en_pg11
&eth_txd0_pg13
&eth_txd1_pg14>;
pinctrl-names = "default";
phy-connection-type = "rmii";
phy-handle = <&eth_phy>;
};
&mdio {
status = "okay";
pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
pinctrl-names = "default";
eth_phy: ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0x00>;
};
};
&sdmmc2 {

4
boards/st/stm32h573i_dk/stm32h573i_dk.dts
View file

@ -167,6 +167,7 @@
&eth_txd1_pg12>;
pinctrl-names = "default";
phy-connection-type = "rmii";
phy-handle = <&eth_phy>;
};
&mdio {
@ -174,10 +175,9 @@
pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
pinctrl-names = "default";
ethernet-phy@0 {
eth_phy: ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0x00>;
status = "okay";
};
};

4
boards/st/stm32h735g_disco/stm32h735g_disco.dts
View file

@ -139,6 +139,7 @@
&eth_txd1_pb13>;
pinctrl-names = "default";
phy-connection-type = "rmii";
phy-handle = <&eth_phy>;
status = "okay";
};
@ -147,10 +148,9 @@
pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
pinctrl-names = "default";
ethernet-phy@0 {
eth_phy: ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0x00>;
status = "okay";
};
};

4
boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7.dts
View file

@ -145,6 +145,7 @@
&eth_rx_er_pi10>;
pinctrl-names = "default";
phy-connection-type = "mii";
phy-handle = <&eth_phy>;
};
&mdio {
@ -152,10 +153,9 @@
pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
pinctrl-names = "default";
ethernet-phy@1 {
eth_phy: ethernet-phy@1 {
compatible = "ethernet-phy";
reg = <0x01>;
status = "okay";
};
};

4
boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.dts
View file

@ -145,6 +145,7 @@
&eth_txd1_pg12>;
pinctrl-names = "default";
phy-connection-type = "rmii";
phy-handle = <&eth_phy>;
};
&mdio {
@ -152,10 +153,9 @@
pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
pinctrl-names = "default";
ethernet-phy@0 {
eth_phy: ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0x00>;
status = "okay";
};
};

4
boards/st/stm32h757i_eval/stm32h757i_eval_stm32h757xx_m7.dts
View file

@ -161,6 +161,7 @@
&eth_txd1_pg12>;
pinctrl-names = "default";
phy-connection-type = "rmii";
phy-handle = <&eth_phy>;
};
&mdio {
@ -168,10 +169,9 @@
pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
pinctrl-names = "default";
ethernet-phy@0 {
eth_phy: ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0x00>;
status = "okay";
};
};

4
boards/witte/linum/linum.dts
View file

@ -239,6 +239,7 @@ zephyr_udc0: &usbotg_fs {
&eth_txd1_pg14>;
pinctrl-names = "default";
phy-connection-type = "rmii";
phy-handle = <&eth_phy>;
};
&mdio {
@ -246,10 +247,9 @@ zephyr_udc0: &usbotg_fs {
pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
pinctrl-names = "default";
ethernet-phy@0 {
eth_phy: ethernet-phy@0 {
compatible = "microchip,ksz8081";
reg = <0x00>;
status = "okay";
microchip,interface-type = "rmii-25MHz";
};
};

7
dts/arm/st/f1/stm32f107.dtsi
View file

@ -29,6 +29,13 @@
<&rcc STM32_CLOCK(AHB1, 15U)>,
<&rcc STM32_CLOCK(AHB1, 16U)>;
status = "disabled";
mdio: mdio {
compatible = "st,stm32-mdio";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
};
};

7
dts/arm/st/f2/stm32f207.dtsi
View file

@ -21,6 +21,13 @@
<&rcc STM32_CLOCK(AHB1, 27U)>,
<&rcc STM32_CLOCK(AHB1, 28U)>;
status = "disabled";
mdio: mdio {
compatible = "st,stm32-mdio";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
};
};

7
dts/arm/st/f4/stm32f407.dtsi
View file

@ -21,6 +21,13 @@
<&rcc STM32_CLOCK(AHB1, 27U)>,
<&rcc STM32_CLOCK(AHB1, 28U)>;
status = "disabled";
mdio: mdio {
compatible = "st,stm32-mdio";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
};
};

7
dts/arm/st/f7/stm32f745.dtsi
View file

@ -86,6 +86,13 @@
<&rcc STM32_CLOCK(AHB1, 27U)>,
<&rcc STM32_CLOCK(AHB1, 28U)>;
status = "disabled";
mdio: mdio {
compatible = "st,stm32-mdio";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
};