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codeowners: Add code owner for INTEL FPGA Nios V/g

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Add code owner for INTEL FPGA Nios V/g dts, SoC and board.

Signed-off-by: Khor Swee Aun <swee.aun.khor@intel.com>
This commit is contained in:
Khor Swee Aun 2023-06-08 10:39:21 +08:00 • committed by Anas Nashif
commit d7141c96f4
1 changed files with 2 additions and 2 deletions
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4
CODEOWNERS
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@ -179,7 +179,7 @@
/boards/riscv/adp_xc7k_ae350/ @cwshu @kevinwang821020 @jimmyzhe
/boards/riscv/longan_nano/ @soburi
/boards/riscv/neorv32/ @henrikbrixandersen
/boards/riscv/niosv_m/ @sweeaun
/boards/riscv/niosv*/ @sweeaun
/boards/shields/ @erwango
/boards/shields/atmel_rf2xx/ @nandojve
/boards/shields/esp_8266/ @nandojve
@ -531,7 +531,7 @@
/dts/riscv/riscv32-litex-vexriscv.dtsi @mateusz-holenko @kgugala @pgielda
/dts/riscv/starfive/ @rajnesh-kanwal
/dts/riscv/andes/andes_v5* @cwshu @kevinwang821020 @jimmyzhe
/dts/riscv/niosv/niosv-m.dtsi @sweeaun
/dts/riscv/niosv/ @sweeaun
/dts/arm/armv*m.dtsi @galak @ioannisg
/dts/arm/armv7-a.dtsi @ibirnbaum
/dts/arm/armv7-r.dtsi @bbolen @stephanosio