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soc: renesas_rcar: gen3: enable L1 cache and branch prediction

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Use CMSIS abstraction to enable L1 cache and branch prediction.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
This commit is contained in:
Julien Massot 2021-03-15 16:18:28 +01:00 • committed by Anas Nashif
commit d6fd631130
2 changed files with 15 additions and 0 deletions
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1
soc/arm/renesas_rcar/gen3/Kconfig.series
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@ -5,6 +5,7 @@ config SOC_SERIES_RCAR_GEN3
bool "Renesas RCAR Gen3 Cortex R7" bool "Renesas RCAR Gen3 Cortex R7"
select ARM select ARM
select CPU_CORTEX_R7 select CPU_CORTEX_R7
select PLATFORM_SPECIFIC_INIT
select GIC_V2 select GIC_V2
select CPU_HAS_DCLS select CPU_HAS_DCLS
select SOC_FAMILY_RCAR select SOC_FAMILY_RCAR

14
soc/arm/renesas_rcar/gen3/soc.c
View file

@ -27,4 +27,18 @@ static int soc_init(const struct device *arg)
return 0; return 0;
} }
void z_platform_init(void)
{
L1C_DisableCaches();
L1C_DisableBTAC();
/* Invalidate instruction cache and flush branch target cache */
__set_ICIALLU(0);
__DSB();
__ISB();
L1C_EnableCaches();
L1C_EnableBTAC();
}
SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);