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drivers: spi: sam0: Implement DMA async API

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This adds support for the async API for SAM0 SERCOM SPI using
DMA to drive the device.  This implementation does the reload
for both transmit and receive in the receive DMA handler.
Doing this simplifies the implementation but means that the
transmit drains completely, resulting in the SPI clock pausing
between buffers while both are reloaded in the receive handler.

Tested with tests/drivers/spi/spi_loopback and several simple
programs monitored with a logic analyzer.

Signed-off-by: Derek Hageman <hageman@inthat.cloud>
This commit is contained in:
Derek Hageman 2019-03-28 16:11:42 -06:00 • committed by Anas Nashif
commit d68666fc08
5 changed files with 349 additions and 3 deletions
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12
soc/arm/atmel_sam0/samd21/dts_fixup.h
View file

@ -63,31 +63,43 @@
#define DT_SPI_SAM0_SERCOM0_BASE_ADDRESS DT_ATMEL_SAM0_SPI_42000800_BASE_ADDRESS
#define DT_SPI_SAM0_SERCOM0_DIPO DT_ATMEL_SAM0_SPI_42000800_DIPO
#define DT_SPI_SAM0_SERCOM0_DOPO DT_ATMEL_SAM0_SPI_42000800_DOPO
#define DT_SPI_SAM0_SERCOM0_RXDMA DT_ATMEL_SAM0_SPI_42000800_RXDMA
#define DT_SPI_SAM0_SERCOM0_TXDMA DT_ATMEL_SAM0_SPI_42000800_TXDMA
#define DT_SPI_SAM0_SERCOM1_LABEL DT_ATMEL_SAM0_SPI_42000C00_LABEL
#define DT_SPI_SAM0_SERCOM1_BASE_ADDRESS DT_ATMEL_SAM0_SPI_42000C00_BASE_ADDRESS
#define DT_SPI_SAM0_SERCOM1_DIPO DT_ATMEL_SAM0_SPI_42000C00_DIPO
#define DT_SPI_SAM0_SERCOM1_DOPO DT_ATMEL_SAM0_SPI_42000C00_DOPO
#define DT_SPI_SAM0_SERCOM1_RXDMA DT_ATMEL_SAM0_SPI_42000C00_RXDMA
#define DT_SPI_SAM0_SERCOM1_TXDMA DT_ATMEL_SAM0_SPI_42000C00_TXDMA
#define DT_SPI_SAM0_SERCOM2_LABEL DT_ATMEL_SAM0_SPI_42001000_LABEL
#define DT_SPI_SAM0_SERCOM2_BASE_ADDRESS DT_ATMEL_SAM0_SPI_42001000_BASE_ADDRESS
#define DT_SPI_SAM0_SERCOM2_DIPO DT_ATMEL_SAM0_SPI_42001000_DIPO
#define DT_SPI_SAM0_SERCOM2_DOPO DT_ATMEL_SAM0_SPI_42001000_DOPO
#define DT_SPI_SAM0_SERCOM2_RXDMA DT_ATMEL_SAM0_SPI_42001000_RXDMA
#define DT_SPI_SAM0_SERCOM2_TXDMA DT_ATMEL_SAM0_SPI_42001000_TXDMA
#define DT_SPI_SAM0_SERCOM3_LABEL DT_ATMEL_SAM0_SPI_42001400_LABEL
#define DT_SPI_SAM0_SERCOM3_BASE_ADDRESS DT_ATMEL_SAM0_SPI_42001400_BASE_ADDRESS
#define DT_SPI_SAM0_SERCOM3_DIPO DT_ATMEL_SAM0_SPI_42001400_DIPO
#define DT_SPI_SAM0_SERCOM3_DOPO DT_ATMEL_SAM0_SPI_42001400_DOPO
#define DT_SPI_SAM0_SERCOM3_RXDMA DT_ATMEL_SAM0_SPI_42001400_RXDMA
#define DT_SPI_SAM0_SERCOM3_TXDMA DT_ATMEL_SAM0_SPI_42001400_TXDMA
#define DT_SPI_SAM0_SERCOM4_LABEL DT_ATMEL_SAM0_SPI_42001800_LABEL
#define DT_SPI_SAM0_SERCOM4_BASE_ADDRESS DT_ATMEL_SAM0_SPI_42001800_BASE_ADDRESS
#define DT_SPI_SAM0_SERCOM4_DIPO DT_ATMEL_SAM0_SPI_42001800_DIPO
#define DT_SPI_SAM0_SERCOM4_DOPO DT_ATMEL_SAM0_SPI_42001800_DOPO
#define DT_SPI_SAM0_SERCOM4_RXDMA DT_ATMEL_SAM0_SPI_42001800_RXDMA
#define DT_SPI_SAM0_SERCOM4_TXDMA DT_ATMEL_SAM0_SPI_42001800_TXDMA
#define DT_SPI_SAM0_SERCOM5_LABEL DT_ATMEL_SAM0_SPI_42001C00_LABEL
#define DT_SPI_SAM0_SERCOM5_BASE_ADDRESS DT_ATMEL_SAM0_SPI_42001C00_BASE_ADDRESS
#define DT_SPI_SAM0_SERCOM5_DIPO DT_ATMEL_SAM0_SPI_42001C00_DIPO
#define DT_SPI_SAM0_SERCOM5_DOPO DT_ATMEL_SAM0_SPI_42001C00_DOPO
#define DT_SPI_SAM0_SERCOM5_RXDMA DT_ATMEL_SAM0_SPI_42001C00_RXDMA
#define DT_SPI_SAM0_SERCOM5_TXDMA DT_ATMEL_SAM0_SPI_42001C00_TXDMA
#define DT_WDT_SAM0_IRQ DT_ATMEL_SAM0_WATCHDOG_40001000_IRQ_0
#define DT_WDT_SAM0_IRQ_PRIORITY DT_ATMEL_SAM0_WATCHDOG_40001000_IRQ_0_PRIORITY