From d66110bb35d96f7d14a3c23e7f10ee3a993ef634 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Karol=20Laso=C5=84czyk?= Date: Fri, 2 Aug 2024 15:36:03 +0200 Subject: [PATCH] boards: Add support for nRF54L20 PDK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce doc and board description. Signed-off-by: Karol Lasończyk --- boards/nordic/nrf54l20pdk/Kconfig.defconfig | 18 +++ boards/nordic/nrf54l20pdk/Kconfig.nrf54l20pdk | 5 + boards/nordic/nrf54l20pdk/board.cmake | 7 ++ boards/nordic/nrf54l20pdk/board.yml | 5 + boards/nordic/nrf54l20pdk/doc/index.rst | 91 ++++++++++++++ .../nrf54l20pdk/nrf54l20_cpuapp_common.dtsi | 117 ++++++++++++++++++ .../nrf54l20pdk_nrf54l20-common.dtsi | 72 +++++++++++ .../nrf54l20pdk_nrf54l20-pinctrl.dtsi | 24 ++++ .../nrf54l20pdk_nrf54l20_cpuapp.dts | 19 +++ .../nrf54l20pdk_nrf54l20_cpuapp.yaml | 17 +++ .../nrf54l20pdk_nrf54l20_cpuapp_defconfig | 29 +++++ 11 files changed, 404 insertions(+) create mode 100644 boards/nordic/nrf54l20pdk/Kconfig.defconfig create mode 100644 boards/nordic/nrf54l20pdk/Kconfig.nrf54l20pdk create mode 100644 boards/nordic/nrf54l20pdk/board.cmake create mode 100644 boards/nordic/nrf54l20pdk/board.yml create mode 100644 boards/nordic/nrf54l20pdk/doc/index.rst create mode 100644 boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi create mode 100644 boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-common.dtsi create mode 100644 boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-pinctrl.dtsi create mode 100644 boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp.dts create mode 100644 boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp.yaml create mode 100644 boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp_defconfig diff --git a/boards/nordic/nrf54l20pdk/Kconfig.defconfig b/boards/nordic/nrf54l20pdk/Kconfig.defconfig new file mode 100644 index 00000000000..850f69bdda0 --- /dev/null +++ b/boards/nordic/nrf54l20pdk/Kconfig.defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF54L20PDK_NRF54L20_CPUAPP + +config BT_CTLR + default BT + +config ROM_START_OFFSET + default 0x800 if BOOTLOADER_MCUBOOT + +config SOC_NRF54LX_SKIP_CLOCK_CONFIG + default y + +config SOC_NRF54LX_SKIP_GLITCHDETECTOR_DISABLE + default y + +endif # BOARD_NRF54L20PDK_NRF54L20_CPUAPP diff --git a/boards/nordic/nrf54l20pdk/Kconfig.nrf54l20pdk b/boards/nordic/nrf54l20pdk/Kconfig.nrf54l20pdk new file mode 100644 index 00000000000..09809ff7374 --- /dev/null +++ b/boards/nordic/nrf54l20pdk/Kconfig.nrf54l20pdk @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF54L20PDK + select SOC_NRF54L20_ENGA_CPUAPP if BOARD_NRF54L20PDK_NRF54L20_CPUAPP diff --git a/boards/nordic/nrf54l20pdk/board.cmake b/boards/nordic/nrf54l20pdk/board.cmake new file mode 100644 index 00000000000..5d36ac00a3e --- /dev/null +++ b/boards/nordic/nrf54l20pdk/board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=cortex-m33" "--speed=4000") + +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nordic/nrf54l20pdk/board.yml b/boards/nordic/nrf54l20pdk/board.yml new file mode 100644 index 00000000000..717adf8e75e --- /dev/null +++ b/boards/nordic/nrf54l20pdk/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf54l20pdk + vendor: nordic + socs: + - name: nrf54l20 diff --git a/boards/nordic/nrf54l20pdk/doc/index.rst b/boards/nordic/nrf54l20pdk/doc/index.rst new file mode 100644 index 00000000000..2297df5dd41 --- /dev/null +++ b/boards/nordic/nrf54l20pdk/doc/index.rst @@ -0,0 +1,91 @@ +.. _nrf54l20pdk_nrf54l20: + +nRF54L20 PDK +############ + +Overview +******** + +.. note:: + + All software for the nRF54L20 SoC is experimental and hardware availability + is restricted to the participants in the limited sampling program. + +The nRF54L20 Preview Development Kit hardware provides +support for the Nordic Semiconductor nRF54L20 Arm Cortex-M33 CPU and +the following devices: + +* CLOCK +* RRAM +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`GRTC (Global real-time counter)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` + +Hardware +******** + +nRF54L20 PDK has two crystal oscillators: + +* High-frequency 32 MHz crystal oscillator (HFXO) +* Low-frequency 32.768 kHz crystal oscillator (LFXO) + +The crystal oscillators can be configured to use either +internal or external capacitors. + +Supported Features +================== + +The ``nrf54l20pdk/nrf54l20/cpuapp`` board target configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| RRAM | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| GRTC | on-chip | system clock | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Programming and Debugging +************************* + +Applications for the ``nrf54l20pdk/nrf54l20/cpuapp`` board target can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +As an example, this section shows how to build and flash the :ref:`hello_world` +application. + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. + +To build and program the sample to the nRF54L20 PDK, complete the following steps: + +First, connect the nRF54L20 PDK to you computer using the IMCU USB port on the PDK. +Next, build the sample by running the following command: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf54l20pdk/nrf54l20/cpuapp + :goals: build flash + +Testing the LEDs and buttons in the nRF54L20 PDK +************************************************ + +Test the nRF54L20 PDK with a :zephyr:code-sample:`blinky` sample. diff --git a/boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi b/boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi new file mode 100644 index 00000000000..cdf6d62a30a --- /dev/null +++ b/boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* This file is common to the secure and non-secure domain */ + +#include +#include "nrf54l20pdk_nrf54l20-common.dtsi" + +/ { + chosen { + zephyr,console = &uart20; + zephyr,shell-uart = &uart20; + zephyr,uart-mcumgr = &uart20; + zephyr,bt-mon-uart = &uart20; + zephyr,bt-c2h-uart = &uart20; + zephyr,flash-controller = &rram_controller; + zephyr,flash = &cpuapp_rram; + zephyr,bt-hci = &bt_hci_controller; + zephyr,ieee802154 = &ieee802154; + }; +}; + +&cpuapp_sram { + status = "okay"; +}; + +&lfxo { + load-capacitors = "internal"; + load-capacitance-femtofarad = <15500>; +}; + +&hfxo { + load-capacitors = "internal"; + load-capacitance-femtofarad = <15000>; +}; + +&grtc { + owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>; + /* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */ + child-owned-channels = <3 4 7 8 9 10 11>; + status = "okay"; +}; + +&cpuapp_rram { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 DT_SIZE_K(64)>; + }; + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x10000 DT_SIZE_K(449)>; + }; + slot0_ns_partition: partition@80400 { + label = "image-0-nonsecure"; + reg = <0x80400 DT_SIZE_K(449)>; + }; + slot1_partition: partition@f0800 { + label = "image-1"; + reg = <0xf0800 DT_SIZE_K(449)>; + }; + slot1_ns_partition: partition@160c00 { + label = "image-1-nonsecure"; + reg = <0x160c00 DT_SIZE_K(449)>; + }; + }; +}; + +&uart20 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpiote20 { + status = "okay"; +}; + +&gpiote30 { + status = "okay"; +}; + +&radio { + status = "okay"; +}; + +&temp { + status = "okay"; +}; + +&clock { + status = "okay"; +}; + +&bt_hci_controller { + status = "okay"; +}; + +&ieee802154 { + status = "okay"; +}; diff --git a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-common.dtsi b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-common.dtsi new file mode 100644 index 00000000000..c188cd39e93 --- /dev/null +++ b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-common.dtsi @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "nrf54l20pdk_nrf54l20-pinctrl.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + label = "Green LED 0"; + }; + led1: led_1 { + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + label = "Green LED 1"; + }; + led2: led_2 { + gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + label = "Green LED 2"; + }; + led3: led_3 { + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + label = "Green LED 3"; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 0"; + zephyr,code = ; + }; + button1: button_1 { + gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 1"; + zephyr,code = ; + }; + button2: button_2 { + gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 2"; + zephyr,code = ; + }; + button3: button_3 { + gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 3"; + zephyr,code = ; + }; + }; + + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + led3 = &led3; + sw0 = &button0; + sw1 = &button1; + sw2 = &button2; + sw3 = &button3; + watchdog0 = &wdt31; + }; +}; + +&uart20 { + current-speed = <115200>; + pinctrl-0 = <&uart20_default>; + pinctrl-1 = <&uart20_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-pinctrl.dtsi b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-pinctrl.dtsi new file mode 100644 index 00000000000..83aa91d8a34 --- /dev/null +++ b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-pinctrl.dtsi @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + /omit-if-no-ref/ uart20_default: uart20_default { + group1 { + psels = ; + }; + group2 { + psels = ; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ uart20_sleep: uart20_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; +}; diff --git a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp.dts b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp.dts new file mode 100644 index 00000000000..af32bc27eb7 --- /dev/null +++ b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp.dts @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "nrf54l20_cpuapp_common.dtsi" + +/ { + compatible = "nordic,nrf54l20pdk_nrf54l20-cpuapp"; + model = "Nordic nRF54L20 PDK nRF54L20 Application MCU"; + + chosen { + zephyr,code-partition = &slot0_partition; + zephyr,sram = &cpuapp_sram; + }; +}; diff --git a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp.yaml b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp.yaml new file mode 100644 index 00000000000..d11ea0d869f --- /dev/null +++ b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp.yaml @@ -0,0 +1,17 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf54l20pdk/nrf54l20/cpuapp +name: nRF54L20-PDK-nRF54L20-Application +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +sysbuild: true +ram: 512 +flash: 449 +supported: + - counter + - gpio diff --git a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp_defconfig b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp_defconfig new file mode 100644 index 00000000000..02796a1361e --- /dev/null +++ b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp_defconfig @@ -0,0 +1,29 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# MPU-based null-pointer dereferencing detection cannot +# be applied as the (0x0 - 0x400) is unmapped for this target. +CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y + +# Enable Cache +CONFIG_CACHE_MANAGEMENT=y +CONFIG_EXTERNAL_CACHE=y + +# Start SYSCOUNTER on driver init +CONFIG_NRF_GRTC_START_SYSCOUNTER=y