From d65149e210529a2196e1d0aa85747e33a1d41f48 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20J=C3=A4ger?= <martin@libre.solar>
Date: Tue, 29 Apr 2025 22:32:29 +0200
Subject: [PATCH] dts: arm: stm32g0: add pwr node and wkup-pins
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WKUP3 is only available for g0b0/1 and g0c1 variants.

WKUP5 is only available in larger packages. However, package sizes
are currently not considered in the devicetree file schema for STM32.

Signed-off-by: Martin Jäger <martin@libre.solar>
---
 dts/arm/st/g0/stm32g0.dtsi   | 42 ++++++++++++++++++++++++++++++++++++
 dts/arm/st/g0/stm32g0b0.dtsi |  7 ++++++
 dts/arm/st/g0/stm32g0b1.dtsi |  7 ++++++
 3 files changed, 56 insertions(+)

diff --git a/dts/arm/st/g0/stm32g0.dtsi b/dts/arm/st/g0/stm32g0.dtsi
index 69a6c8863da..1bd4a243fe9 100644
--- a/dts/arm/st/g0/stm32g0.dtsi
+++ b/dts/arm/st/g0/stm32g0.dtsi
@@ -16,6 +16,7 @@
 #include <zephyr/dt-bindings/dma/stm32_dma.h>
 #include <zephyr/dt-bindings/adc/adc.h>
 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
+#include <zephyr/dt-bindings/power/stm32_pwr.h>
 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
 #include <zephyr/dt-bindings/reset/stm32g0_reset.h>
 #include <freq.h>
@@ -448,6 +449,47 @@
 			dma-requests= <49>;
 			status = "disabled";
 		};
+
+		pwr: power@40007000 {
+			compatible = "st,stm32-pwr";
+			reg = <0x40007000 0x400>; /* PWR register bank */
+			status = "disabled";
+
+			wkup-pins-nb = <6>; /* 6 system wake-up pins */
+			wkup-pins-pol;
+			wkup-pins-pupd;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			wkup-pin@1 {
+				reg = <0x1>;
+				wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_PIN_NOT_MUXED>;
+			};
+
+			wkup-pin@2 {
+				reg = <0x2>;
+				wkup-gpios = <&gpioa 4 STM32_PWR_WKUP_PIN_NOT_MUXED>,
+					     <&gpioc 13 STM32_PWR_WKUP_PIN_NOT_MUXED>;
+			};
+
+			/* wkup-pin@3 only available for g0b0/1 and g0c1 variants */
+
+			wkup-pin@4 {
+				reg = <0x4>;
+				wkup-gpios = <&gpioa 2 STM32_PWR_WKUP_PIN_NOT_MUXED>;
+			};
+
+			wkup-pin@5 {
+				reg = <0x5>;
+				wkup-gpios = <&gpioc 5 STM32_PWR_WKUP_PIN_NOT_MUXED>;
+			};
+
+			wkup-pin@6 {
+				reg = <0x6>;
+				wkup-gpios = <&gpiob 5 STM32_PWR_WKUP_PIN_NOT_MUXED>;
+			};
+		};
 	};
 
 	die_temp: dietemp {
diff --git a/dts/arm/st/g0/stm32g0b0.dtsi b/dts/arm/st/g0/stm32g0b0.dtsi
index 9e8477c33ad..02488820600 100644
--- a/dts/arm/st/g0/stm32g0b0.dtsi
+++ b/dts/arm/st/g0/stm32g0b0.dtsi
@@ -105,6 +105,13 @@
 				 <&rcc STM32_SRC_HSI48 USB_SEL(0)>;
 			status = "disabled";
 		};
+
+		pwr: power@40007000 {
+			wkup-pin@3 {
+				reg = <0x3>;
+				wkup-gpios = <&gpioe 6 STM32_PWR_WKUP_PIN_NOT_MUXED>;
+			};
+		};
 	};
 
 	usb_fs_phy: usbphy {
diff --git a/dts/arm/st/g0/stm32g0b1.dtsi b/dts/arm/st/g0/stm32g0b1.dtsi
index 4a1bb1065f4..2bf7c1dd753 100644
--- a/dts/arm/st/g0/stm32g0b1.dtsi
+++ b/dts/arm/st/g0/stm32g0b1.dtsi
@@ -149,6 +149,13 @@
 				 <&rcc STM32_SRC_HSI48 USB_SEL(0)>;
 			status = "disabled";
 		};
+
+		pwr: power@40007000 {
+			wkup-pin@3 {
+				reg = <0x3>;
+				wkup-gpios = <&gpioe 6 STM32_PWR_WKUP_PIN_NOT_MUXED>;
+			};
+		};
 	};
 
 	usb_fs_phy: usbphy {