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test: frdm_mcxn947_mcxn947: Add config and overlay for QSPI variant

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Add config and overlay files for the QSPI variant of the
NXP FRDM-MCXN947 board

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This commit is contained in:
Mahesh Mahadevan 2024-05-03 14:27:21 -05:00 • committed by Anas Nashif
commit d5ae219799
9 changed files with 175 additions and 0 deletions
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4
boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.yaml
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@ -15,11 +15,15 @@ toolchain:
- gnuarmemb
- xtools
supported:
- can
- dma
- gpio
- spi
- i2c
- watchdog
- pwm
- counter
- sdhc
- regulator
- usb_device
vendor: nxp

36
tests/drivers/adc/adc_api/boards/frdm_mcxn947_mcxn947_cpu0_qspi.overlay Normal file
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@ -0,0 +1,36 @@
/*
* Copyright 2024 NXP
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/dt-bindings/adc/adc.h>
#include <zephyr/dt-bindings/adc/mcux-lpadc.h>
/ {
zephyr,user {
io-channels = <&lpadc0 0>, <&lpadc0 1>;
};
};
&lpadc0 {
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
zephyr,gain = "ADC_GAIN_1";
zephyr,reference = "ADC_REF_EXTERNAL1";
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
zephyr,resolution = <12>;
zephyr,input-positive = <MCUX_LPADC_CH1A>;
};
channel@1 {
reg = <1>;
zephyr,gain = "ADC_GAIN_1";
zephyr,reference = "ADC_REF_EXTERNAL1";
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
zephyr,resolution = <12>;
zephyr,input-positive = <MCUX_LPADC_CH2A>;
};
};

1
tests/drivers/can/timing/boards/frdm_mcxn947_mcxn947_cpu0_qspi.conf Normal file
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@ -0,0 +1 @@
CONFIG_TEST_ALL_BITRATES=y

1
tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn947_mcxn947_cpu0_qspi.conf Normal file
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@ -0,0 +1 @@
CONFIG_I2C_VIRTUAL=n

51
tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn947_mcxn947_cpu0_qspi.overlay Normal file
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@ -0,0 +1,51 @@
/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
&pinctrl {
pinmux_flexcomm1_lpi2c: pinmux_flexcomm1_lpi2c {
group0 {
pinmux = <FC1_P0_PIO0_24>,
<FC1_P1_PIO0_25>;
slew-rate = "fast";
drive-strength = "low";
input-enable;
bias-pull-up;
drive-open-drain;
};
};
};
&flexcomm1 {
status = "okay";
};
/* We cannot enable SPI and I2C on the same flexcomm */
&flexcomm1_lpspi1 {
status = "disabled";
};
/* To test this sample, connect
* LPI2C1 SCL(J2-12, P1_25/FC1_P1) --> LPI2C2 SCL(J2-20, P4_1/FC2_P1)
* LPI2C1 SDA(J2-8, P1_24/FC1_P0) --> LPI2C2 SDA(J2-18, P4_0/FC2_P0)
*/
&flexcomm1_lpi2c1 {
pinctrl-0 = <&pinmux_flexcomm1_lpi2c>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_STANDARD>;
status = "okay";
eeprom0: eeprom@54 {
compatible = "zephyr,i2c-target-eeprom";
reg = <0x54>;
size = <1024>;
};
};
&flexcomm2_lpi2c2 {
eeprom1: eeprom@56 {
compatible = "zephyr,i2c-target-eeprom";
reg = <0x56>;
size = <1024>;
};
};

47
tests/drivers/regulator/voltage/boards/frdm_mcxn947_mcxn947_cpu0_qspi.overlay Normal file
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@ -0,0 +1,47 @@
/*
* Copyright 2024 NXP
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/dt-bindings/adc/adc.h>
#include <zephyr/dt-bindings/adc/mcux-lpadc.h>
#include <zephyr/dt-bindings/regulator/nxp_vref.h>
/* To do this test, connect LPADC0 channel 2A(J8 pin 28) to VREF_OUT (TP1) */
/ {
resources: resources {
compatible = "test-regulator-voltage";
regulators = <&vref>;
tolerance-microvolt = <10000>;
set-read-delay-ms = <1>;
adc-avg-count = <10>;
io-channels = <&lpadc0 0>;
min-microvolt = <1000000>;
max-microvolt = <2100000>;
};
};
&vref {
regulator-initial-mode = <NXP_VREF_MODE_INTERNAL_REGULATOR>;
};
&lpadc0 {
#address-cells = <1>;
#size-cells = <0>;
/* In this case, the LPADC reference source cannot be set to VREFO,
* switch the reference source to VDD_ANA.
*/
voltage-ref= <2>;
channel@0 {
reg = <0>;
zephyr,gain = "ADC_GAIN_1";
zephyr,reference = "ADC_REF_EXTERNAL0";
zephyr,vref-mv = <3300>;
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
zephyr,resolution = <12>;
zephyr,input-positive = <MCUX_LPADC_CH2A>;
};
};

7
tests/drivers/spi/spi_loopback/boards/frdm_mcxn947_mcxn947_cpu0_qspi.conf Normal file
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@ -0,0 +1,7 @@
#
# Copyright 2024 NXP
#
# SPDX-License-Identifier: Apache-2.0
#
CONFIG_SPI_MCUX_LPSPI_DMA=y
CONFIG_SPI_ASYNC=n

19
tests/drivers/spi/spi_loopback/boards/frdm_mcxn947_mcxn947_cpu0_qspi.overlay Normal file
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@ -0,0 +1,19 @@
/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Connect J2-10 and J2-8 */
&flexcomm1_lpspi1 {
slow@0 {
compatible = "test-spi-loopback-slow";
reg = <0>;
spi-max-frequency = <500000>;
};
fast@0 {
compatible = "test-spi-loopback-fast";
reg = <0>;
spi-max-frequency = <16000000>;
};
};

9
tests/drivers/uart/uart_async_api/boards/frdm_mcxn947_mcxn947_cpu0_qspi.overlay Normal file
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@ -0,0 +1,9 @@
/*
* Copyright 2024 NXP
* SPDX-License-Identifier: Apache-2.0
*/
/*
* To test this sample connect P4_2(J1-4) to P4_3(J1-2)
*/
dut: &flexcomm2_lpuart2 {};