drivers: esp32: uart: use hal functions
In order to have Espressif SoCs working with the same uart drivers, all low level functions are now replaced to hal_espressif HAL calls. This also changes pinmux, gpio and uart init order to meet its dependencies. Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This commit is contained in:
Sylvio Alves
Christopher Friedt
parent
56ef5aac52
commit
d5aa5c2a77
18 changed files with 250 additions and 377 deletions
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@ -11,18 +11,22 @@
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#ifdef CONFIG_SOC_ESP32
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#include <esp32/rom/ets_sys.h>
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#include <esp32/rom/gpio.h>
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#include <soc/dport_reg.h>
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#elif defined(CONFIG_SOC_ESP32S2)
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#include <esp32s2/rom/ets_sys.h>
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#include <esp32s2/rom/gpio.h>
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#include <soc/dport_reg.h>
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#elif defined(CONFIG_SOC_ESP32C3)
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#include <esp32c3/rom/ets_sys.h>
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#include <esp32c3/rom/gpio.h>
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#endif
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#include <soc/uart_struct.h>
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#include <soc/dport_access.h>
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#include "stubs.h"
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#include <hal/uart_ll.h>
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#include <hal/uart_hal.h>
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#include <hal/uart_types.h>
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#include <drivers/gpio.h>
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#include <soc/gpio_sig_map.h>
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#include <soc/uart_reg.h>
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@ -46,25 +50,20 @@
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#define ISR_HANDLER intr_handler_t
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#endif
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struct uart_esp32_pin {
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const char *gpio_name;
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int signal;
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int pin;
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};
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struct uart_esp32_config {
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struct uart_device_config dev_conf;
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uart_hal_context_t hal;
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const struct device *clock_dev;
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const struct {
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int tx_out;
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int rx_in;
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int rts_out;
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int cts_in;
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} signals;
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const struct {
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int tx;
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int rx;
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int rts;
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int cts;
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} pins;
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const struct uart_esp32_pin tx;
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const struct uart_esp32_pin rx;
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const struct uart_esp32_pin rts;
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const struct uart_esp32_pin cts;
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const clock_control_subsys_t clock_subsys;
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@ -82,11 +81,9 @@ struct uart_esp32_data {
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};
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#define DEV_CFG(dev) \
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((const struct uart_esp32_config *const)(dev)->config)
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((struct uart_esp32_config *const)(dev)->config)
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#define DEV_DATA(dev) \
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((struct uart_esp32_data *)(dev)->data)
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#define DEV_BASE(dev) \
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((volatile uart_dev_t *)(DEV_CFG(dev))->dev_conf.base)
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#define UART_FIFO_LIMIT (UART_LL_FIFO_DEF_LEN)
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#define UART_TX_FIFO_THRESH 0x1
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@ -99,30 +96,33 @@ static void uart_esp32_isr(void *arg);
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static int uart_esp32_poll_in(const struct device *dev, unsigned char *p_char)
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{
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if (DEV_BASE(dev)->status.rxfifo_cnt == 0) {
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int inout_rd_len = 1;
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if (uart_hal_get_rxfifo_len(&DEV_CFG(dev)->hal) == 0) {
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return -1;
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}
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uart_ll_read_rxfifo(DEV_BASE(dev), p_char, 1);
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return 0;
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uart_hal_read_rxfifo(&DEV_CFG(dev)->hal, p_char, &inout_rd_len);
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return inout_rd_len;
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}
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static IRAM_ATTR void uart_esp32_poll_out(const struct device *dev,
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unsigned char c)
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static void uart_esp32_poll_out(const struct device *dev, unsigned char c)
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{
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uint32_t written;
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/* Wait for space in FIFO */
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while ((UART_FIFO_LIMIT - DEV_BASE(dev)->status.txfifo_cnt) <= 0) {
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while (uart_hal_get_txfifo_len(&DEV_CFG(dev)->hal) == 0) {
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; /* Wait */
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}
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/* Send a character */
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uart_ll_write_txfifo(DEV_BASE(dev), &c, 1);
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uart_hal_write_txfifo(&DEV_CFG(dev)->hal, &c, 1, &written);
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}
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static int uart_esp32_err_check(const struct device *dev)
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{
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uint32_t err = DEV_BASE(dev)->int_st.parity_err
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| DEV_BASE(dev)->int_st.frm_err;
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uint32_t mask = uart_hal_get_intsts_mask(&DEV_CFG(dev)->hal);
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uint32_t err = mask & (UART_INTR_PARITY_ERR | UART_INTR_FRAM_ERR);
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return err;
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}
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@ -131,101 +131,153 @@ static int uart_esp32_err_check(const struct device *dev)
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static int uart_esp32_config_get(const struct device *dev,
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struct uart_config *cfg)
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{
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struct uart_esp32_data *data = DEV_DATA(dev);
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uart_parity_t parity;
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uart_stop_bits_t stop_bit;
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uart_word_length_t data_bit;
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uart_hw_flowcontrol_t hw_flow;
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cfg->baudrate = data->uart_config.baudrate;
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uart_hal_get_baudrate(&DEV_CFG(dev)->hal, &cfg->baudrate);
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if (DEV_BASE(dev)->conf0.parity_en) {
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cfg->parity = DEV_BASE(dev)->conf0.parity;
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} else {
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uart_hal_get_parity(&DEV_CFG(dev)->hal, &parity);
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switch (parity) {
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case UART_PARITY_DISABLE:
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cfg->parity = UART_CFG_PARITY_NONE;
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break;
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case UART_PARITY_EVEN:
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cfg->parity = UART_CFG_PARITY_EVEN;
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break;
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case UART_PARITY_ODD:
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cfg->parity = UART_CFG_PARITY_ODD;
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break;
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default:
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return -ENOTSUP;
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}
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cfg->stop_bits = DEV_BASE(dev)->conf0.stop_bit_num;
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cfg->data_bits = DEV_BASE(dev)->conf0.bit_num;
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uart_hal_get_stop_bits(&DEV_CFG(dev)->hal, &stop_bit);
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switch (stop_bit) {
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case UART_STOP_BITS_1:
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cfg->stop_bits = UART_CFG_STOP_BITS_1;
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break;
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case UART_STOP_BITS_1_5:
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cfg->stop_bits = UART_CFG_STOP_BITS_1_5;
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break;
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case UART_STOP_BITS_2:
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cfg->stop_bits = UART_CFG_STOP_BITS_2;
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break;
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default:
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return -ENOTSUP;
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}
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if (DEV_BASE(dev)->conf0.tx_flow_en) {
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uart_hal_get_data_bit_num(&DEV_CFG(dev)->hal, &data_bit);
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switch (data_bit) {
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case UART_DATA_5_BITS:
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cfg->data_bits = UART_CFG_DATA_BITS_5;
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break;
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case UART_DATA_6_BITS:
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cfg->data_bits = UART_CFG_DATA_BITS_6;
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break;
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case UART_DATA_7_BITS:
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cfg->data_bits = UART_CFG_DATA_BITS_7;
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break;
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case UART_DATA_8_BITS:
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cfg->data_bits = UART_CFG_DATA_BITS_8;
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break;
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default:
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return -ENOTSUP;
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}
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uart_hal_get_hw_flow_ctrl(&DEV_CFG(dev)->hal, &hw_flow);
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switch (hw_flow) {
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case UART_HW_FLOWCTRL_DISABLE:
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cfg->flow_ctrl = UART_CFG_FLOW_CTRL_NONE;
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break;
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case UART_HW_FLOWCTRL_CTS_RTS:
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cfg->flow_ctrl = UART_CFG_FLOW_CTRL_RTS_CTS;
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break;
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default:
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return -ENOTSUP;
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}
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if (DEV_BASE(dev)->conf1.rx_flow_en) {
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cfg->flow_ctrl = UART_CFG_FLOW_CTRL_DTR_DSR;
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}
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return 0;
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}
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#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
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static int uart_esp32_set_baudrate(const struct device *dev, int baudrate)
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{
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uart_ll_set_baudrate(DEV_BASE(dev), baudrate);
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return 1;
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}
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static int uart_esp32_configure_pins(const struct device *dev)
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static int uart_esp32_configure_pins(const struct device *dev, const struct uart_config *uart)
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{
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const struct uart_esp32_config *const cfg = DEV_CFG(dev);
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esp_rom_gpio_matrix_out(cfg->pins.tx,
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cfg->signals.tx_out,
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false,
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false);
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do {
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if (cfg->tx.gpio_name == NULL || cfg->rx.gpio_name == NULL)
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break;
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esp_rom_gpio_matrix_in(cfg->pins.rx,
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cfg->signals.rx_in,
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false);
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/* TX pin config */
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const struct device *tx_dev = device_get_binding(cfg->tx.gpio_name);
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if (cfg->pins.cts) {
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esp_rom_gpio_matrix_out(cfg->pins.cts,
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cfg->signals.cts_in,
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false,
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false);
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}
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if (!tx_dev)
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break;
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gpio_pin_set(tx_dev, cfg->tx.pin, 1);
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gpio_pin_configure(tx_dev, cfg->tx.pin, GPIO_OUTPUT);
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esp_rom_gpio_matrix_out(cfg->tx.pin, cfg->tx.signal, 0, 0);
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if (cfg->pins.rts) {
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esp_rom_gpio_matrix_in(cfg->pins.rts,
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cfg->signals.rts_out,
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false);
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}
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/* RX pin config */
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const struct device *rx_dev = device_get_binding(cfg->rx.gpio_name);
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return 0;
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if (!rx_dev)
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break;
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gpio_pin_configure(rx_dev, cfg->rx.pin, GPIO_PULL_UP | GPIO_INPUT);
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esp_rom_gpio_matrix_in(cfg->rx.pin, cfg->rx.signal, 0);
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if (uart->flow_ctrl == UART_CFG_FLOW_CTRL_RTS_CTS) {
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if (cfg->rts.gpio_name == NULL || cfg->cts.gpio_name == NULL)
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break;
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/* CTS pin config */
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const struct device *cts_dev = device_get_binding(cfg->cts.gpio_name);
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if (!cts_dev)
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break;
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gpio_pin_configure(cts_dev, cfg->cts.pin, GPIO_PULL_UP | GPIO_INPUT);
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esp_rom_gpio_matrix_in(cfg->cts.pin, cfg->cts.signal, 0);
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/* RTS pin config */
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const struct device *rts_dev = device_get_binding(cfg->rts.gpio_name);
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if (!rts_dev)
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break;
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gpio_pin_configure(rts_dev, cfg->rts.pin, GPIO_OUTPUT);
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esp_rom_gpio_matrix_out(cfg->rts.pin, cfg->rts.signal, 0, 0);
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}
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return 0;
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} while (0);
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return -EINVAL;
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}
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static int uart_esp32_configure(const struct device *dev,
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const struct uart_config *cfg)
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static int uart_esp32_configure(const struct device *dev, const struct uart_config *cfg)
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{
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int ret = uart_esp32_configure_pins(dev, cfg);
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#ifndef CONFIG_SOC_ESP32C3
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/* this register does not exist for esp32c3 uart controller */
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DEV_BASE(dev)->conf0.tick_ref_always_on = 1;
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#endif
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if (ret < 0) {
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return ret;
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}
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DEV_BASE(dev)->conf1.rxfifo_full_thrhd = UART_RX_FIFO_THRESH;
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DEV_BASE(dev)->conf1.txfifo_empty_thrhd = UART_TX_FIFO_THRESH;
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uart_esp32_configure_pins(dev);
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clock_control_on(DEV_CFG(dev)->clock_dev, DEV_CFG(dev)->clock_subsys);
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/*
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* Reset RX Buffer by reading all received bytes
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* Hardware Reset functionality can't be used with UART 1/2
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*/
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while (DEV_BASE(dev)->status.rxfifo_cnt != 0) {
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uint8_t c;
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uart_ll_read_rxfifo(DEV_BASE(dev), &c, 1);
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}
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uart_hal_set_sclk(&DEV_CFG(dev)->hal, UART_SCLK_APB);
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uart_hal_set_rxfifo_full_thr(&DEV_CFG(dev)->hal, UART_RX_FIFO_THRESH);
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uart_hal_set_txfifo_empty_thr(&DEV_CFG(dev)->hal, UART_TX_FIFO_THRESH);
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uart_hal_rxfifo_rst(&DEV_CFG(dev)->hal);
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switch (cfg->parity) {
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case UART_CFG_PARITY_NONE:
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DEV_BASE(dev)->conf0.parity = 0;
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DEV_BASE(dev)->conf0.parity_en = 0;
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uart_hal_set_parity(&DEV_CFG(dev)->hal, UART_PARITY_DISABLE);
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break;
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case UART_CFG_PARITY_EVEN:
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DEV_BASE(dev)->conf0.parity_en = 1;
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uart_hal_set_parity(&DEV_CFG(dev)->hal, UART_PARITY_EVEN);
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break;
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case UART_CFG_PARITY_ODD:
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DEV_BASE(dev)->conf0.parity = 1;
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DEV_BASE(dev)->conf0.parity_en = 1;
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uart_hal_set_parity(&DEV_CFG(dev)->hal, UART_PARITY_ODD);
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break;
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default:
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return -ENOTSUP;
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@ -233,47 +285,56 @@ static int uart_esp32_configure(const struct device *dev,
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switch (cfg->stop_bits) {
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case UART_CFG_STOP_BITS_1:
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uart_hal_set_stop_bits(&DEV_CFG(dev)->hal, UART_STOP_BITS_1);
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break;
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case UART_CFG_STOP_BITS_1_5:
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uart_hal_set_stop_bits(&DEV_CFG(dev)->hal, UART_STOP_BITS_1_5);
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break;
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case UART_CFG_STOP_BITS_2:
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DEV_BASE(dev)->conf0.stop_bit_num = cfg->stop_bits;
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uart_hal_set_stop_bits(&DEV_CFG(dev)->hal, UART_STOP_BITS_2);
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break;
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default:
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return -ENOTSUP;
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}
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if (cfg->data_bits <= UART_CFG_DATA_BITS_8) {
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DEV_BASE(dev)->conf0.bit_num = cfg->data_bits;
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} else {
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switch (cfg->data_bits) {
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case UART_CFG_DATA_BITS_5:
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uart_hal_set_data_bit_num(&DEV_CFG(dev)->hal, UART_DATA_5_BITS);
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break;
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case UART_CFG_DATA_BITS_6:
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uart_hal_set_data_bit_num(&DEV_CFG(dev)->hal, UART_DATA_6_BITS);
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break;
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case UART_CFG_DATA_BITS_7:
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uart_hal_set_data_bit_num(&DEV_CFG(dev)->hal, UART_DATA_7_BITS);
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break;
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case UART_CFG_DATA_BITS_8:
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uart_hal_set_data_bit_num(&DEV_CFG(dev)->hal, UART_DATA_8_BITS);
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break;
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default:
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return -ENOTSUP;
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}
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switch (cfg->flow_ctrl) {
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case UART_CFG_FLOW_CTRL_NONE:
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DEV_BASE(dev)->conf0.tx_flow_en = 0;
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DEV_BASE(dev)->conf1.rx_flow_en = 0;
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uart_hal_set_hw_flow_ctrl(&DEV_CFG(dev)->hal, UART_HW_FLOWCTRL_DISABLE, 0);
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break;
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case UART_CFG_FLOW_CTRL_RTS_CTS:
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DEV_BASE(dev)->conf0.tx_flow_en = 1;
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DEV_BASE(dev)->conf1.rx_flow_en = 1;
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uart_hal_set_hw_flow_ctrl(&DEV_CFG(dev)->hal, UART_HW_FLOWCTRL_CTS_RTS, 10);
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break;
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default:
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return -ENOTSUP;
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}
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if (uart_esp32_set_baudrate(dev, cfg->baudrate)) {
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DEV_DATA(dev)->uart_config.baudrate = cfg->baudrate;
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} else {
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return -ENOTSUP;
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}
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uart_hal_set_baudrate(&DEV_CFG(dev)->hal, cfg->baudrate);
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uart_ll_set_rx_tout(DEV_BASE(dev), 0x16);
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uart_hal_set_rx_timeout(&DEV_CFG(dev)->hal, 0x16);
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return 0;
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}
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static int uart_esp32_init(const struct device *dev)
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{
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uart_esp32_configure(dev, &DEV_DATA(dev)->uart_config);
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int ret = uart_esp32_configure(dev, &DEV_DATA(dev)->uart_config);
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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DEV_DATA(dev)->irq_line =
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@ -283,7 +344,7 @@ static int uart_esp32_init(const struct device *dev)
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(void *)dev,
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NULL);
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#endif
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return 0;
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return ret;
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}
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@ -292,74 +353,78 @@ static int uart_esp32_init(const struct device *dev)
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static int uart_esp32_fifo_fill(const struct device *dev,
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const uint8_t *tx_data, int len)
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{
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int space = UART_FIFO_LIMIT - DEV_BASE(dev)->status.txfifo_cnt;
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uint32_t written = 0;
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space = MIN(len, space);
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uart_ll_write_txfifo(DEV_BASE(dev), tx_data, space);
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return space;
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uart_hal_write_txfifo(&DEV_CFG(dev)->hal, tx_data, len, &written);
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return written;
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}
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|
||||
static int uart_esp32_fifo_read(const struct device *dev,
|
||||
uint8_t *rx_data, const int len)
|
||||
{
|
||||
const int num_rx = DEV_BASE(dev)->status.rxfifo_cnt;
|
||||
const int num_rx = uart_hal_get_rxfifo_len(&DEV_CFG(dev)->hal);
|
||||
int read = MIN(len, num_rx);
|
||||
|
||||
uart_ll_read_rxfifo(DEV_BASE(dev), rx_data, num_rx);
|
||||
return num_rx;
|
||||
if (!read) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
uart_hal_read_rxfifo(&DEV_CFG(dev)->hal, rx_data, &read);
|
||||
return read;
|
||||
}
|
||||
|
||||
static void uart_esp32_irq_tx_enable(const struct device *dev)
|
||||
{
|
||||
DEV_BASE(dev)->int_clr.txfifo_empty = 1;
|
||||
DEV_BASE(dev)->int_ena.txfifo_empty = 1;
|
||||
uart_hal_clr_intsts_mask(&DEV_CFG(dev)->hal, UART_INTR_TXFIFO_EMPTY);
|
||||
uart_hal_ena_intr_mask(&DEV_CFG(dev)->hal, UART_INTR_TXFIFO_EMPTY);
|
||||
}
|
||||
|
||||
static void uart_esp32_irq_tx_disable(const struct device *dev)
|
||||
{
|
||||
DEV_BASE(dev)->int_ena.txfifo_empty = 0;
|
||||
uart_hal_disable_intr_mask(&DEV_CFG(dev)->hal, UART_INTR_TXFIFO_EMPTY);
|
||||
}
|
||||
|
||||
static int uart_esp32_irq_tx_ready(const struct device *dev)
|
||||
{
|
||||
return (DEV_BASE(dev)->status.txfifo_cnt < UART_FIFO_LIMIT);
|
||||
return (uart_hal_get_txfifo_len(&DEV_CFG(dev)->hal) > 0);
|
||||
}
|
||||
|
||||
static void uart_esp32_irq_rx_enable(const struct device *dev)
|
||||
{
|
||||
DEV_BASE(dev)->int_clr.rxfifo_full = 1;
|
||||
DEV_BASE(dev)->int_clr.rxfifo_tout = 1;
|
||||
DEV_BASE(dev)->int_ena.rxfifo_full = 1;
|
||||
DEV_BASE(dev)->int_ena.rxfifo_tout = 1;
|
||||
uart_hal_clr_intsts_mask(&DEV_CFG(dev)->hal, UART_INTR_RXFIFO_FULL);
|
||||
uart_hal_clr_intsts_mask(&DEV_CFG(dev)->hal, UART_INTR_RXFIFO_TOUT);
|
||||
uart_hal_ena_intr_mask(&DEV_CFG(dev)->hal, UART_INTR_RXFIFO_FULL);
|
||||
uart_hal_ena_intr_mask(&DEV_CFG(dev)->hal, UART_INTR_RXFIFO_TOUT);
|
||||
}
|
||||
|
||||
static void uart_esp32_irq_rx_disable(const struct device *dev)
|
||||
{
|
||||
DEV_BASE(dev)->int_ena.rxfifo_full = 0;
|
||||
DEV_BASE(dev)->int_ena.rxfifo_tout = 0;
|
||||
uart_hal_disable_intr_mask(&DEV_CFG(dev)->hal, UART_INTR_RXFIFO_FULL);
|
||||
uart_hal_disable_intr_mask(&DEV_CFG(dev)->hal, UART_INTR_RXFIFO_TOUT);
|
||||
}
|
||||
|
||||
static int uart_esp32_irq_tx_complete(const struct device *dev)
|
||||
{
|
||||
/* check if TX FIFO is empty */
|
||||
return (DEV_BASE(dev)->status.txfifo_cnt == 0 ? 1 : 0);
|
||||
return (uart_hal_get_txfifo_len(&DEV_CFG(dev)->hal) == UART_LL_FIFO_DEF_LEN ? 1 : 0);
|
||||
}
|
||||
|
||||
static int uart_esp32_irq_rx_ready(const struct device *dev)
|
||||
{
|
||||
return (DEV_BASE(dev)->status.rxfifo_cnt > 0);
|
||||
return (uart_hal_get_rxfifo_len(&DEV_CFG(dev)->hal) > 0);
|
||||
}
|
||||
|
||||
static void uart_esp32_irq_err_enable(const struct device *dev)
|
||||
{
|
||||
/* enable framing, parity */
|
||||
DEV_BASE(dev)->int_ena.frm_err = 1;
|
||||
DEV_BASE(dev)->int_ena.parity_err = 1;
|
||||
uart_hal_ena_intr_mask(&DEV_CFG(dev)->hal, UART_INTR_FRAM_ERR);
|
||||
uart_hal_ena_intr_mask(&DEV_CFG(dev)->hal, UART_INTR_PARITY_ERR);
|
||||
}
|
||||
|
||||
static void uart_esp32_irq_err_disable(const struct device *dev)
|
||||
{
|
||||
DEV_BASE(dev)->int_ena.frm_err = 0;
|
||||
DEV_BASE(dev)->int_ena.parity_err = 0;
|
||||
uart_hal_disable_intr_mask(&DEV_CFG(dev)->hal, UART_INTR_FRAM_ERR);
|
||||
uart_hal_disable_intr_mask(&DEV_CFG(dev)->hal, UART_INTR_PARITY_ERR);
|
||||
}
|
||||
|
||||
static int uart_esp32_irq_is_pending(const struct device *dev)
|
||||
|
|
@ -369,9 +434,10 @@ static int uart_esp32_irq_is_pending(const struct device *dev)
|
|||
|
||||
static int uart_esp32_irq_update(const struct device *dev)
|
||||
{
|
||||
DEV_BASE(dev)->int_clr.rxfifo_full = 1;
|
||||
DEV_BASE(dev)->int_clr.rxfifo_tout = 1;
|
||||
DEV_BASE(dev)->int_clr.txfifo_empty = 1;
|
||||
uart_hal_clr_intsts_mask(&DEV_CFG(dev)->hal, UART_INTR_RXFIFO_FULL);
|
||||
uart_hal_clr_intsts_mask(&DEV_CFG(dev)->hal, UART_INTR_RXFIFO_TOUT);
|
||||
uart_hal_clr_intsts_mask(&DEV_CFG(dev)->hal, UART_INTR_TXFIFO_EMPTY);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
|
@ -387,6 +453,12 @@ static void uart_esp32_isr(void *arg)
|
|||
{
|
||||
const struct device *dev = (const struct device *)arg;
|
||||
struct uart_esp32_data *data = DEV_DATA(dev);
|
||||
uint32_t uart_intr_status = uart_hal_get_intsts_mask(&DEV_CFG(dev)->hal);
|
||||
|
||||
if (uart_intr_status == 0) {
|
||||
return;
|
||||
}
|
||||
uart_hal_clr_intsts_mask(&DEV_CFG(dev)->hal, uart_intr_status);
|
||||
|
||||
/* Verify if the callback has been registered */
|
||||
if (data->irq_cb) {
|
||||
|
|
@ -422,39 +494,49 @@ static const DRAM_ATTR struct uart_driver_api uart_esp32_api = {
|
|||
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
|
||||
};
|
||||
|
||||
#define GPIO0_NAME COND_CODE_1(DT_NODE_HAS_STATUS(DT_NODELABEL(gpio0), okay), \
|
||||
(DT_LABEL(DT_INST(0, espressif_esp32_gpio))), (NULL))
|
||||
#define GPIO1_NAME COND_CODE_1(DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay), \
|
||||
(DT_LABEL(DT_INST(1, espressif_esp32_gpio))), (NULL))
|
||||
|
||||
#define DT_UART_ESP32_GPIO_NAME(idx, pin) ( \
|
||||
DT_INST_PROP(idx, pin) < 32 ? GPIO0_NAME : GPIO1_NAME)
|
||||
|
||||
#define ESP32_UART_INIT(idx) \
|
||||
static const DRAM_ATTR struct uart_esp32_config uart_esp32_cfg_port_##idx = { \
|
||||
.dev_conf = { \
|
||||
.base = \
|
||||
(uint8_t *)DT_REG_ADDR(DT_NODELABEL(uart##idx)), \
|
||||
.hal = { \
|
||||
.dev = \
|
||||
(uart_dev_t *)DT_REG_ADDR(DT_NODELABEL(uart##idx)), \
|
||||
}, \
|
||||
\
|
||||
.clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_NODELABEL(uart##idx))), \
|
||||
\
|
||||
.signals = { \
|
||||
.tx_out = U##idx##TXD_OUT_IDX, \
|
||||
.rx_in = U##idx##RXD_IN_IDX, \
|
||||
.rts_out = U##idx##RTS_OUT_IDX, \
|
||||
.cts_in = U##idx##CTS_IN_IDX, \
|
||||
}, \
|
||||
\
|
||||
.pins = { \
|
||||
.tx = DT_PROP(DT_NODELABEL(uart##idx), tx_pin), \
|
||||
.rx = DT_PROP(DT_NODELABEL(uart##idx), rx_pin), \
|
||||
IF_ENABLED( \
|
||||
DT_PROP(DT_NODELABEL(uart##idx), hw_flow_control), \
|
||||
(.rts = DT_PROP(DT_NODELABEL(uart##idx), rts_pin), \
|
||||
.cts = DT_PROP(DT_NODELABEL(uart##idx), cts_pin), \
|
||||
)) \
|
||||
}, \
|
||||
\
|
||||
.tx = { \
|
||||
.signal = U##idx##TXD_OUT_IDX, \
|
||||
.pin = DT_INST_PROP(idx, tx_pin), \
|
||||
.gpio_name = DT_UART_ESP32_GPIO_NAME(idx, tx_pin), \
|
||||
}, \
|
||||
.rx = { \
|
||||
.signal = U##idx##RXD_IN_IDX, \
|
||||
.pin = DT_INST_PROP(idx, rx_pin), \
|
||||
.gpio_name = DT_UART_ESP32_GPIO_NAME(idx, rx_pin), \
|
||||
}, \
|
||||
IF_ENABLED(DT_PROP(DT_NODELABEL(uart##idx), hw_flow_control), ( \
|
||||
.rts = { \
|
||||
.signal = U##idx##RTS_OUT_IDX, \
|
||||
.pin = DT_INST_PROP(idx, rts_pin), \
|
||||
.gpio_name = DT_UART_ESP32_GPIO_NAME(idx, rts_pin), \
|
||||
}, \
|
||||
.cts = { \
|
||||
.signal = U##idx##CTS_IN_IDX, \
|
||||
.pin = DT_INST_PROP(idx, cts_pin), \
|
||||
.gpio_name = DT_UART_ESP32_GPIO_NAME(idx, cts_pin), \
|
||||
},)) \
|
||||
.clock_subsys = (clock_control_subsys_t)DT_CLOCKS_CELL(DT_NODELABEL(uart##idx), offset), \
|
||||
.irq_source = DT_IRQN(DT_NODELABEL(uart##idx)) \
|
||||
}; \
|
||||
\
|
||||
static struct uart_esp32_data uart_esp32_data_##idx = { \
|
||||
.uart_config = { \
|
||||
.baudrate = DT_PROP(DT_NODELABEL(uart##idx), current_speed),\
|
||||
.baudrate = DT_INST_PROP(idx, current_speed),\
|
||||
.parity = UART_CFG_PARITY_NONE, \
|
||||
.stop_bits = UART_CFG_STOP_BITS_1, \
|
||||
.data_bits = UART_CFG_DATA_BITS_8, \
|
||||
|
|
@ -469,7 +551,7 @@ DEVICE_DT_DEFINE(DT_NODELABEL(uart##idx), \
|
|||
NULL, \
|
||||
&uart_esp32_data_##idx, \
|
||||
&uart_esp32_cfg_port_##idx, \
|
||||
PRE_KERNEL_1, \
|
||||
POST_KERNEL, \
|
||||
CONFIG_SERIAL_INIT_PRIORITY, \
|
||||
&uart_esp32_api);
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue