arch: arm64: add public header for asm macros

Move generic macros to exported assembly header file
'macro.inc'. Rename the existing 'macro.inc' to 'macro_priv.inc'.

Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
This commit is contained in:
Sandeep Tripathy 2020-04-27 16:56:29 +05:30 committed by Andrew Boie
commit d4f1f2a07e
7 changed files with 56 additions and 40 deletions

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@ -14,7 +14,7 @@
#include <offsets_short.h>
#include <arch/cpu.h>
#include <sw_isr_table.h>
#include "macro.inc"
#include "macro_priv.inc"
_ASM_FILE_PROLOGUE

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@ -4,43 +4,10 @@
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _MACRO_H_
#define _MACRO_H_
#ifndef _MACRO_PRIV_INC_
#define _MACRO_PRIV_INC_
#ifdef _ASMLANGUAGE
/*
* macro to support mov of immediate constant to 64 bit register
* It will generate instruction sequence of 'mov'/ 'movz' and one
* to three 'movk' depending on the immediate value.
*/
.macro mov_imm, xreg, imm
.if ((\imm) == 0)
mov \xreg, \imm
.else
.if (((\imm) >> 31) == 0 || ((\imm) >> 31) == 0x1ffffffff)
movz \xreg, (\imm >> 16) & 0xffff, lsl 16
.else
.if (((\imm) >> 47) == 0 || ((\imm) >> 47) == 0x1ffff)
movz \xreg, (\imm >> 32) & 0xffff, lsl 32
.else
movz \xreg, (\imm >> 48) & 0xffff, lsl 48
movk \xreg, (\imm >> 32) & 0xffff, lsl 32
.endif
movk \xreg, (\imm >> 16) & 0xffff, lsl 16
.endif
movk \xreg, (\imm) & 0xffff, lsl 0
.endif
.endm
.macro switch_el, xreg, el3_label, el2_label, el1_label
mrs \xreg, CurrentEL
cmp \xreg, 0xc
beq \el3_label
cmp \xreg, 0x8
beq \el2_label
cmp \xreg, 0x4
beq \el1_label
.endm
/**
* @brief Save volatile registers
@ -157,4 +124,4 @@
#endif /* _ASMLANGUAGE */
#endif /* _MACRO_H_ */
#endif /* _MACRO_PRIV_INC_ */

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@ -15,7 +15,7 @@
#include <linker/sections.h>
#include <arch/cpu.h>
#include "vector_table.h"
#include "macro.inc"
#include "macro_priv.inc"
_ASM_FILE_PROLOGUE

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@ -17,7 +17,7 @@
#include <offsets_short.h>
#include <arch/cpu.h>
#include <syscall.h>
#include "macro.inc"
#include "macro_priv.inc"
_ASM_FILE_PROLOGUE

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@ -11,8 +11,9 @@
#include <toolchain.h>
#include <linker/sections.h>
#include <arch/cpu.h>
#include "vector_table.h"
#include "macro.inc"
#include "macro_priv.inc"
_ASM_FILE_PROLOGUE

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@ -25,6 +25,7 @@
#include <arch/arm/aarch64/misc.h>
#include <arch/arm/aarch64/asm_inline.h>
#include <arch/arm/aarch64/cpu.h>
#include <arch/arm/aarch64/macro.inc>
#include <arch/arm/aarch64/sys_io.h>
#include <arch/arm/aarch64/timer.h>
#include <arch/common/addr_types.h>

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@ -0,0 +1,47 @@
/*
* Copyright 2020 Broadcom.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_MACRO_INC_
#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_MACRO_INC_
#ifdef _ASMLANGUAGE
.macro switch_el, xreg, el3_label, el2_label, el1_label
mrs \xreg, CurrentEL
cmp \xreg, 0xc
beq \el3_label
cmp \xreg, 0x8
beq \el2_label
cmp \xreg, 0x4
beq \el1_label
.endm
/*
* macro to support mov of immediate constant to 64 bit register
* It will generate instruction sequence of 'mov'/ 'movz' and one
* to three 'movk' depending on the immediate value.
*/
.macro mov_imm, xreg, imm
.if ((\imm) == 0)
mov \xreg, \imm
.else
.if (((\imm) >> 31) == 0 || ((\imm) >> 31) == 0x1ffffffff)
movz \xreg, (\imm >> 16) & 0xffff, lsl 16
.else
.if (((\imm) >> 47) == 0 || ((\imm) >> 47) == 0x1ffff)
movz \xreg, (\imm >> 32) & 0xffff, lsl 32
.else
movz \xreg, (\imm >> 48) & 0xffff, lsl 48
movk \xreg, (\imm >> 32) & 0xffff, lsl 32
.endif
movk \xreg, (\imm >> 16) & 0xffff, lsl 16
.endif
movk \xreg, (\imm) & 0xffff, lsl 0
.endif
.endm
#endif /* _ASMLANGUAGE */
#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_MACRO_INC_ */