boards: riscv: Add INTEL Nios V/g General Processor board

Add board support for INTEL Nios V/g General Processor.

Signed-off-by: Khor Swee Aun <swee.aun.khor@intel.com>

boards/riscv/niosv_g/Kconfig.board

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+# Copyright (C) 2023, Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_NIOSV_G
+	bool "Intel FPGA Nios V/g General Purpose Processor"
+	depends on SOC_NIOSV_G

boards/riscv/niosv_g/Kconfig.defconfig

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+# Copyright (C) 2023, Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_NIOSV_G
+
+config BOARD
+	default "niosv_g"
+
+endif # BOARD_NIOSV_G

boards/riscv/niosv_g/doc/index.rst

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+.. _niosv_g:
+
+INTEL FPGA niosv_g
+####################
+
+Overview
+********
+
+niosv_g board is based on Intel FPGA Design Store Nios® V/g Hello World Example Design system and this complete system is consisted of following IP blocks:
+
+.. code-block:: console
+
+	Nios® V/g Processor Intel® FPGA IP
+	JTAG UART Intel® FPGA IP
+	On-Chip Memory Intel® FPGA IP
+
+Nios® V/g hello world example design system
+===========================================
+
+Prebuilt Nios® V/g hello world example design system is available in Intel FPGA Design store.
+- https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/design-store.html?s=Newest
+
+For example, Arria10 Nios® V/g processor example design system prebuilt files can be downloaded from following link.
+- https://www.intel.com/content/www/us/en/design-example/776196/intel-arria-10-fpga-hello-world-design-on-nios-v-g-processor.html
+
+ready_to_test/top.sof file is the prebuilt SRAM Object File for hello world example design system after the downloaded PAR files extracted successfully.
+
+Create Nios® V/g processor example design system in FPGA
+========================================================
+
+Please use Intel Quartus Programmer tool to program Nios® V/g processor based system into the FPGA and execute application.
+
+In order to create the Nios® V/g processor inside the FPGA device, please download the generated .sof file onto the board with the following command.
+
+.. code-block:: console
+
+	quartus_pgm -c 1 -m JTAG -o "p;top.sof@1"
+
+.. code-block:: console
+
+	Note:
+	-c 1 is referring to JTAG cable number connected to the Host Computer.
+	@1 is referring to device index on the JTAG Chain and may differ for your board.
+	top.sof is referring to Nios® V/m processor based system SRAM Object File.
+
+Download Zephyr elf file and run application
+============================================
+
+To download the Zephyr Executable and Linkable Format .elf file, please use the niosv-download command within Nios V Command Shell environment.
+
+.. code-block:: console
+
+	niosv-download -g <elf file>
+
+Use the JTAG UART terminal to print the stdout and stderr of the Nios® V/g processor system.
+
+.. code-block:: console
+
+	juart-terminal
+
+Similar message shown below should be appeared in the JTAG UART terminal when using hello world sample code:
+
+.. code-block:: console
+
+	*** Booting Zephyr OS build zephyr-vn.n.nn  ***
+	Hello World! niosv_g

boards/riscv/niosv_g/niosv_g.dts

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+/*
+ * Copyright (C) 2023, Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <niosv/niosv-g.dtsi>
+
+/ {
+	model = "niosv_g";
+	compatible = "intel,niosv_g";
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,sram = &sram0;
+	};
+};
+
+&cpu0 {
+	clock-frequency = <50000000>;
+};
+
+&sram0 {
+	reg = <0x0 0x40000>;
+};
+
+&mtimer {
+	reg = <0x90000 0x10>;
+};
+
+&uart0 {
+	reg = <0x90078 0x8>;
+	status = "okay";
+};

boards/riscv/niosv_g/niosv_g.yaml

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+identifier: niosv_g
+name: INTEL FPGA Nios V/g general purpose processor
+type: mcu
+arch: riscv32
+toolchain:
+  - zephyr
+ram: 256

boards/riscv/niosv_g/niosv_g_defconfig

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+# Copyright (C) 2023, Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SOC_SERIES_NIOSV=y
+CONFIG_SOC_NIOSV_G=y
+CONFIG_BOARD_NIOSV_G=y
+CONFIG_CONSOLE=y
+CONFIG_PRINTK=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_XIP=n