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dts: drivers: Add DTS MBOX entry for NXP MCXN947

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This commit adds MBOX device tree entry for MCXN947.
Adds support for MCXN in NXP ipm and mbox drivers.

Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
This commit is contained in:
Tomas Galbicka 2024-11-26 08:45:22 +01:00 • committed by Benjamin Cabé
commit d4d180c216
5 changed files with 49 additions and 8 deletions
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9
drivers/ipm/ipm_mcux.c
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2017-2018, NXP * Copyright (c) 2017-2018, 2024 NXP
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -20,8 +20,11 @@
#define MCUX_IPM_DATA_REGS 1 #define MCUX_IPM_DATA_REGS 1
#define MCUX_IPM_MAX_ID_VAL 0 #define MCUX_IPM_MAX_ID_VAL 0
#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) #if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES) || \
#ifdef LPC55S69_cm33_core0_SERIES defined(CONFIG_SOC_SERIES_MCXN))
#if (defined(LPC55S69_cm33_core0_SERIES) || defined(MCXN947_cm33_core0_SERIES) || \
defined(MCXN946_cm33_core0_SERIES) || defined(MCXN547_cm33_core0_SERIES) || \
defined(MCXN546_cm33_core0_SERIES))
#define MAILBOX_ID_THIS_CPU kMAILBOX_CM33_Core0 #define MAILBOX_ID_THIS_CPU kMAILBOX_CM33_Core0
#define MAILBOX_ID_OTHER_CPU kMAILBOX_CM33_Core1 #define MAILBOX_ID_OTHER_CPU kMAILBOX_CM33_Core1
#else #else

7
drivers/mbox/mbox_nxp_mailbox.c
View file

@ -21,8 +21,11 @@ LOG_MODULE_REGISTER(nxp_mbox_mailbox);
#define MAILBOX_MAX_CHANNELS 4 #define MAILBOX_MAX_CHANNELS 4
#define MAILBOX_MBOX_SIZE 3 #define MAILBOX_MBOX_SIZE 3
#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) #if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES) || \
#ifdef LPC55S69_cm33_core0_SERIES defined(CONFIG_SOC_SERIES_MCXN))
#if (defined(LPC55S69_cm33_core0_SERIES) || defined(MCXN947_cm33_core0_SERIES) || \
defined(MCXN946_cm33_core0_SERIES) || defined(MCXN547_cm33_core0_SERIES) || \
defined(MCXN546_cm33_core0_SERIES))
#define MAILBOX_ID_THIS_CPU kMAILBOX_CM33_Core0 #define MAILBOX_ID_THIS_CPU kMAILBOX_CM33_Core0
#define MAILBOX_ID_OTHER_CPU kMAILBOX_CM33_Core1 #define MAILBOX_ID_OTHER_CPU kMAILBOX_CM33_Core1
#else #else

9
dts/arm/nxp/nxp_mcxn94x_common.dtsi
View file

@ -534,6 +534,15 @@
}; };
}; };
mbox: mbox@b2000 {
compatible = "nxp,mbox-mailbox";
reg = <0xb2000 0xec>;
interrupts = <54 0>;
rx-channels = <4>;
#mbox-cells = <1>;
status = "disabled";
};
edma0: dma-controller@80000 { edma0: dma-controller@80000 {
#dma-cells = <2>; #dma-cells = <2>;
compatible = "nxp,mcux-edma"; compatible = "nxp,mcux-edma";

11
soc/nxp/mcx/mcxn/Kconfig
View file

@ -7,9 +7,6 @@ config SOC_SERIES_MCXN
select ARM select ARM
select HAS_MCUX select HAS_MCUX
select HAS_MCUX_FLEXCOMM select HAS_MCUX_FLEXCOMM
select CPU_CORTEX_M_HAS_SYSTICK
select CPU_CORTEX_M_HAS_DWT
select SOC_RESET_HOOK
config SOC_MCXN947_CPU0 config SOC_MCXN947_CPU0
select CPU_CORTEX_M33 select CPU_CORTEX_M33
@ -17,8 +14,16 @@ config SOC_MCXN947_CPU0
select CPU_HAS_ARM_MPU select CPU_HAS_ARM_MPU
select CPU_HAS_FPU select CPU_HAS_FPU
select ARMV8_M_DSP select ARMV8_M_DSP
select SOC_RESET_HOOK
select ARM_TRUSTZONE_M select ARM_TRUSTZONE_M
select HAS_MCUX_CACHE select HAS_MCUX_CACHE
select CPU_CORTEX_M_HAS_SYSTICK
select CPU_CORTEX_M_HAS_DWT
config SOC_MCXN947_CPU1
select CPU_CORTEX_M33
select CPU_CORTEX_M_HAS_SYSTICK
select CPU_CORTEX_M_HAS_DWT
config SOC_MCXN236 config SOC_MCXN236
select CPU_CORTEX_M33 select CPU_CORTEX_M33

21
soc/nxp/mcx/mcxn/soc.c
View file

@ -38,3 +38,24 @@ void soc_reset_hook(void)
* Throw a build error if user is enabling SPI and UART/I2C on a Flexcomm node. * Throw a build error if user is enabling SPI and UART/I2C on a Flexcomm node.
*/ */
DT_FOREACH_STATUS_OKAY(nxp_lpspi, FLEXCOMM_CHECK) DT_FOREACH_STATUS_OKAY(nxp_lpspi, FLEXCOMM_CHECK)
#if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_SOC_MCXN947_CPU0)
/* This function is also called at deep sleep resume. */
static int second_core_boot(void)
{
/* Boot source for Core 1 from flash */
SYSCON->CPBOOT = ((uint32_t)(char *)DT_REG_ADDR(DT_CHOSEN(zephyr_code_cpu1_partition)) &
SYSCON_CPBOOT_CPBOOT_MASK);
uint32_t temp = SYSCON->CPUCTRL;
temp |= 0xc0c40000U;
SYSCON->CPUCTRL = temp | SYSCON_CPUCTRL_CPU1RSTEN_MASK | SYSCON_CPUCTRL_CPU1CLKEN_MASK;
SYSCON->CPUCTRL = (temp | SYSCON_CPUCTRL_CPU1CLKEN_MASK) & (~SYSCON_CPUCTRL_CPU1RSTEN_MASK);
return 0;
}
SYS_INIT(second_core_boot, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
#endif