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boards: st: stm32h745i_disco: Use PLL2Q as FDCAN clock source

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With this configuration of the device tree, we use 80 MHz as
a FDCAN bus clock. This configuration allows to pass the tests.

Signed-off-by: Tomáš Juřena <jurenatomas@gmail.com>
This commit is contained in:
Tomáš Juřena 2024-05-15 20:40:02 +02:00 • committed by Johan Hedberg
commit d477c66909
2 changed files with 15 additions and 0 deletions
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14
boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7.dts
View file

@ -72,6 +72,16 @@
status = "okay";
};
&pll2 {
div-m = <5>;
mul-n = <192>;
div-p = <2>;
div-q = <12>;
div-r = <4>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(480)>;
@ -202,6 +212,8 @@
status = "okay";
pinctrl-0 = <&fdcan1_tx_ph13 &fdcan1_rx_ph14>;
pinctrl-names = "default";
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>,
<&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>;
sample-point = <875>;
sample-point-data = <875>;
@ -214,6 +226,8 @@
status = "okay";
pinctrl-0 = <&fdcan2_tx_pb13 &fdcan2_rx_pb5>;
pinctrl-names = "default";
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>,
<&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>;
sample-point = <875>;
sample-point-data = <875>;

1
boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7.yaml
View file

@ -20,4 +20,5 @@ supported:
- memc
- spi
- rtc
- can
vendor: st