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dts: arm: st: rename STM32 FDCAN devicetree node labels

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Rename the STM32 FDCAN node labels to match to naming used in the ST
reference manuals. This also matches the naming used in the STM32 FDCAN
pinctrl macros.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This commit is contained in:
Henrik Brix Andersen 2023-08-15 11:09:22 +02:00 • committed by Carles Cufí
commit d45cbc8d2e
12 changed files with 15 additions and 15 deletions
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4
boards/arm/nucleo_g0b1re/nucleo_g0b1re.dts
View file

@ -21,7 +21,7 @@
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
zephyr,canbus = &can1;
zephyr,canbus = &fdcan1;
};
leds {
@ -174,7 +174,7 @@ zephyr_udc0: &usb {
pinctrl-names = "default";
};
&can1 {
&fdcan1 {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00001000>,
<&rcc STM32_SRC_PLL_Q FDCAN_SEL(1)>;
pinctrl-0 = <&fdcan1_rx_pa11 &fdcan1_tx_pa12>;

4
boards/arm/nucleo_g474re/nucleo_g474re.dts
View file

@ -19,7 +19,7 @@
zephyr,shell-uart = &lpuart1;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,canbus = &can1;
zephyr,canbus = &fdcan1;
};
leds {
@ -202,7 +202,7 @@
status = "okay";
};
&can1 {
&fdcan1 {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>,
<&rcc STM32_SRC_HSE FDCAN_SEL(0)>;
pinctrl-0 = <&fdcan1_rx_pa11 &fdcan1_tx_pa12>;

2
boards/arm/nucleo_u575zi_q/nucleo_u575zi_q-common.dtsi
View file

@ -167,7 +167,7 @@
status = "okay";
};
&can1 {
&fdcan1 {
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>,
<&rcc STM32_SRC_PLL1_Q FDCAN1_SEL(1)>;
pinctrl-0 = <&fdcan1_rx_pd0 &fdcan1_tx_pd1>;

2
boards/arm/nucleo_u575zi_q/nucleo_u575zi_q.dts
View file

@ -19,7 +19,7 @@
zephyr,shell-uart = &usart1;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,canbus = &can1;
zephyr,canbus = &fdcan1;
};
aliases {

4
boards/arm/stm32h573i_dk/stm32h573i_dk.dts
View file

@ -20,7 +20,7 @@
zephyr,sram = &sram1;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
zephyr,canbus = &can1;
zephyr,canbus = &fdcan1;
};
leds {
@ -216,7 +216,7 @@
status = "okay";
};
&can1 {
&fdcan1 {
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>,
<&rcc STM32_SRC_PLL1_Q FDCAN_SEL(1)>;
pinctrl-0 = <&fdcan1_rx_pa11 &fdcan1_tx_pa12>;

2
dts/arm/st/g0/stm32g0b1.dtsi
View file

@ -30,7 +30,7 @@
};
};
can1: can@40006400 {
fdcan1: can@40006400 {
compatible = "st,stm32-fdcan";
reg = <0x40006400 0x400>, <0x4000b400 0x350>;
reg-names = "m_can", "message_ram";

2
dts/arm/st/g4/stm32g4.dtsi
View file

@ -383,7 +383,7 @@
status = "disabled";
};
can1: can@40006400 {
fdcan1: can@40006400 {
compatible = "st,stm32-fdcan";
reg = <0x40006400 0x400>, <0x4000a400 0x350>;
reg-names = "m_can", "message_ram";

2
dts/arm/st/g4/stm32g473.dtsi
View file

@ -94,7 +94,7 @@
status = "disabled";
};
can3: can@40006c00 {
fdcan3: can@40006c00 {
compatible = "st,stm32-fdcan";
reg = <0x40006c00 0x400>, <0x4000a400 0x9f0>;
reg-names = "m_can", "message_ram";

2
dts/arm/st/g4/stm32g491.dtsi
View file

@ -10,7 +10,7 @@
soc {
compatible = "st,stm32g491", "st,stm32g4", "simple-bus";
can2: can@40006800 {
fdcan2: can@40006800 {
compatible = "st,stm32-fdcan";
reg = <0x40006800 0x400>, <0x4000a400 0x6a0>;
reg-names = "m_can", "message_ram";

2
dts/arm/st/h5/stm32h5.dtsi
View file

@ -436,7 +436,7 @@
status = "disabled";
};
can1: can@4000a400 {
fdcan1: can@4000a400 {
compatible = "st,stm32-fdcan";
reg = <0x4000a400 0x400>, <0x4000ac00 0x350>;
reg-names = "m_can", "message_ram";

2
dts/arm/st/h5/stm32h562.dtsi
View file

@ -293,7 +293,7 @@
status = "disabled";
};
can2: can@4000a800 {
fdcan2: can@4000a800 {
compatible = "st,stm32-fdcan";
reg = <0x4000a800 0x400>, <0x4000ac00 0x6a0>;
reg-names = "m_can", "message_ram";

2
dts/arm/st/u5/stm32u5.dtsi
View file

@ -771,7 +771,7 @@
num-sampling-time-common-channels = <2>;
};
can1: can@4000a400 {
fdcan1: can@4000a400 {
compatible = "st,stm32-fdcan";
reg = <0x4000a400 0x400>, <0x4000ac00 0x350>;
reg-names = "m_can", "message_ram";