From d426d122f14b8de17900c776be3306099ec7f7bd Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 23 Jun 2017 14:17:11 -0500 Subject: [PATCH] boards; cc2650_sensortag: Get building with sanitycheck Board port was done before the yaml transition, so was missing a cc2650_sensortag.yaml. As such when we build all the test we get a few build errors that we also fixed up. Signed-off-by: Kumar Gala --- arch/arm/soc/ti_simplelink/cc2650/soc.c | 4 ++++ boards/arm/cc2650_sensortag/cc2650_sensortag.yaml | 8 ++++++++ 2 files changed, 12 insertions(+) create mode 100644 boards/arm/cc2650_sensortag/cc2650_sensortag.yaml diff --git a/arch/arm/soc/ti_simplelink/cc2650/soc.c b/arch/arm/soc/ti_simplelink/cc2650/soc.c index f8eec419a5d..7b934e54ad4 100644 --- a/arch/arm/soc/ti_simplelink/cc2650/soc.c +++ b/arch/arm/soc/ti_simplelink/cc2650/soc.c @@ -66,9 +66,11 @@ ti_ccfg[CCFG_SIZE / sizeof(u32_t)] = { static const u32_t clkloadctl = REG_ADDR(TI_CC2650_PRCM_40082000_BASE_ADDRESS, CC2650_PRCM_CLKLOADCTL); +#ifdef CONFIG_CC2650_TRNG_RANDOM_GENERATOR static const u32_t secdmaclkgr = REG_ADDR(TI_CC2650_PRCM_40082000_BASE_ADDRESS, CC2650_PRCM_SECDMACLKGR); +#endif static const u32_t gpioclkgr = REG_ADDR(TI_CC2650_PRCM_40082000_BASE_ADDRESS, CC2650_PRCM_GPIOCLKGR); @@ -78,9 +80,11 @@ static const u32_t pdctl0 = static const u32_t pdstat0 = REG_ADDR(TI_CC2650_PRCM_40082000_BASE_ADDRESS, CC2650_PRCM_PDSTAT0); +#ifdef CONFIG_SERIAL static const u32_t uartclkgr = REG_ADDR(TI_CC2650_PRCM_40082000_BASE_ADDRESS, CC2650_PRCM_UARTCLKGR); +#endif /* Setup power and clock for needed hardware modules. */ static void setup_modules_prcm(void) diff --git a/boards/arm/cc2650_sensortag/cc2650_sensortag.yaml b/boards/arm/cc2650_sensortag/cc2650_sensortag.yaml new file mode 100644 index 00000000000..2f7d6e9af17 --- /dev/null +++ b/boards/arm/cc2650_sensortag/cc2650_sensortag.yaml @@ -0,0 +1,8 @@ +identifier: cc2650_sensortag +name: SimpleLink multi-standard CC2650 SensorTag kit +type: mcu +arch: arm +toolchain: + - zephyr + - gccarmemb +ram: 20