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Microchip: MEC172x clock control driver

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Implement a clock control driver for Microchip MEC172x handling
configuring the 32 KHz input sources for the PLL and peripheral-32k
clock domains. MEC172x differs from MEC152x. MEC152x had one 32K source
for both PLL and peripherals. MEC172x allows the two domains to use
independent 32 KHz sources. Device tree updated to provide addresses
of hardware used by the driver.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
This commit is contained in:
Scott Worley 2021-07-19 14:14:20 -04:00 • committed by Christopher Friedt
commit d3f6b54f8e
14 changed files with 882 additions and 0 deletions
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24
include/drivers/clock_control/mchp_xec_clock_control.h Normal file
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/*
* Copyright (c) 2021 Microchip Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_MCHP_XEC_H_
#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_MCHP_XEC_H_
#include <drivers/clock_control.h>
#include <dt-bindings/clock/mchp_xec_pcr.h>
/*
* Set/clear Microchip XEC peripheral sleep enable.
* SoC layer contains the chip specific sleep index and positions
*/
int z_mchp_xec_pcr_periph_sleep(uint8_t slp_idx, uint8_t slp_pos,
uint8_t slp_en);
#if defined(CONFIG_PM)
void mchp_xec_clk_ctrl_sys_sleep_enable(bool is_deep);
void mchp_xec_clk_ctrl_sys_sleep_disable(void);
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_LPC11U6X_CLOCK_CONTROL_H_ */

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include/dt-bindings/clock/mchp_xec_pcr.h Normal file
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/*
* Copyright (c) 2021 Microchip Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCHP_XEC_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCHP_XEC_H_
/* PLL and Peripheral 32 KHz clock source */
#define MCHP_XEC_CLK32K_SRC_SIL_OSC 0U
#define MCHP_XEC_CLK32K_SRC_XTAL 1U
#define MCHP_XEC_CLK32K_SRC_PIN 2U
/* Crystal connection */
#define MCHP_XEC_XTAL_PARALLEL 0U
#define MCHP_XEC_XTAL_SINGLE_ENDED 1U
/*
* When the 32KHz pin goes down fall back
* to either internal silicon oscillator
* or crystal.
*/
#define MCHP_XEC_PIN32K_FB_SIL_OSC 0U
#define MCHP_XEC_PIN32K_FB_XTAL 1U
/* clocks supported by the driver */
#define MCHP_XEC_PCR_CLK_CORE 0
#define MCHP_XEC_PCR_CLK_CPU 1
#define MCHP_XEC_PCR_CLK_BUS 2
#define MCHP_XEC_PCR_CLK_PERIPH 3
#define MCHP_XEC_PCR_CLK_PERIPH_FAST 4
#define MCHP_XEC_PCR_CLK_PERIPH_SLOW 5
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCHP_XEC_H_ */