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drivers: adc: add LPADC driver support to mimxrt685 platform

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Add LPADC support to the mimxrt685 platform.

Signed-off-by: David Leach <david.leach@nxp.com>
This commit is contained in:
David Leach 2021-08-19 16:07:40 -05:00 • committed by Anas Nashif
commit d3cd0d2f9a
10 changed files with 142 additions and 3 deletions
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2
boards/arm/mimxrt685_evk/doc/index.rst
View file

@ -95,6 +95,8 @@ features:
+-----------+------------+-------------------------------------+
| USB | on-chip | USB device |
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc |
+-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:

4
boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.dts
View file

@ -303,6 +303,10 @@ i2s1: &flexcomm3 {
pwr-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
};
&lpadc0 {
status = "okay";
};
zephyr_udc0: &usbhs {
status = "okay";
};

87
boards/arm/mimxrt685_evk/pinmux.c
View file

@ -961,6 +961,93 @@ static int mimxrt685_evk_pinmux_init(const struct device *dev)
IOPCTL_PinMuxSet(IOPCTL, 2U, 9U, port2_pin9_config);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpadc0), okay) && CONFIG_ADC
/*
* The current test and sample applications uses a single channel for
* testing so we only need to enable the pin for that single use.
*
* If your application requires more then the mappings are as follows
* for the rt685_evk:
*
* +---------+------+---------+-------+
* | Port# | ADC |Schematic|Arduino|
* | pin | Chn# | |header |
* +---------+------+---------+-------+
* | PIO0_5 | CH0A | ADC0_0 | J30.1 |
* +---------+------+---------+-------+
* | PIO0_6 | CH0B | ADC0_8 | J30.2 |
* +---------+------+---------+-------+
* | PIO0_12 | CH1A | ADC0_1 | |
* +---------+------+---------+-------+
* | PIO0_13 | CH1B | ADC0_9 | |
* +---------+------+---------+-------+
* | PIO0_19 | CH2A | ADC0_2 | J30.3 |
* +---------+------+---------+-------+
* | PIO0_20 | CH2B | ADC0_10 | J30.4 |
* +---------+------+---------+-------+
* | PIO0_26 | CH3A | ADC0_3 | |
* +---------+------+---------+-------+
* | PIO0_27 | CH3B | ADC0_11 | |
* +---------+------+---------+-------+
* | PIO1_8 | CH4A | ADC0_4 | |
* +---------+------+---------+-------+
* | PIO1_9 | CH4B | ADC0_12 | |
* +---------+------+---------+-------+
* | PIO3_23 | CH5A | ADC0_5 | |
* +---------+------+---------+-------+
* | PIO3_24 | CH5B | ADC0_13 | |
* +---------+------+---------+-------+
*
* Per the mimxrt6xx reference manual, The channels 0-5 are analong input.
* Optionally, channels 0A through 5A can be paired with channels 0B
* through 5B for differential input on their respective ADC channel.
*
*/
const uint32_t port0_pin5_config = (
/* Pin is configured as ADC0_0 */
IOPCTL_PIO_FUNC0 |
/* Disable pull-up / pull-down function */
IOPCTL_PIO_PUPD_DI |
/* Enable pull-down function */
IOPCTL_PIO_PULLDOWN_EN |
/* Disable input buffer function */
IOPCTL_PIO_INBUF_DI |
/* Normal mode */
IOPCTL_PIO_SLEW_RATE_NORMAL |
/* Normal drive */
IOPCTL_PIO_FULLDRIVE_DI |
/* Analog mux is enabled */
IOPCTL_PIO_ANAMUX_EN |
/* Pseudo Output Drain is disabled */
IOPCTL_PIO_PSEDRAIN_DI |
/* Input function is not inverted */
IOPCTL_PIO_INV_DI);
/* PORT0 PIN5 (coords: F4) is configured as ADC0_0 */
IOPCTL_PinMuxSet(IOPCTL, 0U, 5U, port0_pin5_config);
const uint32_t port0_pin6_config = (
/* Pin is configured as ADC0_8 */
IOPCTL_PIO_FUNC0 |
/* Disable pull-up / pull-down function */
IOPCTL_PIO_PUPD_DI |
/* Enable pull-down function */
IOPCTL_PIO_PULLDOWN_EN |
/* Disable input buffer function */
IOPCTL_PIO_INBUF_DI |
/* Normal mode */
IOPCTL_PIO_SLEW_RATE_NORMAL |
/* Normal drive */
IOPCTL_PIO_FULLDRIVE_DI |
/* Analog mux is enabled */
IOPCTL_PIO_ANAMUX_EN |
/* Pseudo Output Drain is disabled */
IOPCTL_PIO_PSEDRAIN_DI |
/* Input function is not inverted */
IOPCTL_PIO_INV_DI);
/* PORT0 PIN6 (coords: E1) is configured as ADC0_8 */
IOPCTL_PinMuxSet(IOPCTL, 0U, 6U, port0_pin6_config);
#endif
return 0;
}

14
drivers/adc/adc_mcux_lpadc.c
View file

@ -273,11 +273,23 @@ static int mcux_lpadc_init(const struct device *dev)
lpadc_config_t adc_config;
#if !defined(CONFIG_SOC_SERIES_IMX_RT11XX)
#if defined(CONFIG_SOC_SERIES_IMX_RT6XX)
SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_ADC_PD_MASK;
SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_ADC_LP_MASK;
RESET_PeripheralReset(kADC0_RST_SHIFT_RSTn);
CLOCK_AttachClk(kSFRO_to_ADC_CLK);
CLOCK_SetClkDiv(kCLOCK_DivAdcClk, config->clock_div);
#else
CLOCK_SetClkDiv(kCLOCK_DivAdcAsyncClk, config->clock_div, true);
CLOCK_AttachClk(config->clock_source);
/* Power up the ADC */
POWER_DisablePD(kPDRUNCFG_PD_LDOGPADC);
#endif
#endif
LPADC_GetDefaultConfig(&adc_config);
@ -357,7 +369,7 @@ static const struct adc_driver_api mcux_lpadc_driver_api = {
#define ASSERT_WITHIN_RANGE(val, min, max, str) \
BUILD_ASSERT(val >= min && val <= max, str)
#if defined(CONFIG_SOC_SERIES_IMX_RT11XX)
#if defined(CONFIG_SOC_SERIES_IMX_RT11XX) || defined(CONFIG_SOC_SERIES_IMX_RT6XX)
#define TO_LPADC_CLOCK_SOURCE(val) 0
#else
#define TO_LPADC_CLOCK_SOURCE(val) \

16
dts/arm/nxp/nxp_rt6xx_common.dtsi
View file

@ -310,6 +310,22 @@
clocks = <&clkctl1 MCUX_USDHC2_CLK>;
label = "USDHC_2";
};
lpadc0: lpadc@13A0000 {
compatible = "nxp,lpc-lpadc";
reg = <0x13A000 0x304>;
interrupts = <22 0>;
status = "disabled";
clk-divider = <1>;
clk-source = <0>;
voltage-ref= <2>;
calibration-average = <128>;
power-level = <1>;
label = "LPADC_0";
offset-value-a = <10>;
offset-value-b = <10>;
#io-channel-cells = <1>;
};
};
&nvic {

12
samples/drivers/adc/boards/mimxrt685_evk_cm33.overlay Normal file
View file

@ -0,0 +1,12 @@
/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright (c) 2020 Linaro Limited
*/
/ {
zephyr,user {
/* adjust channel number according to pinmux in board.dts */
io-channels = <&lpadc0 0>;
};
};

4
soc/arm/nxp_imx/rt6xx/Kconfig.defconfig.series
View file

@ -27,6 +27,10 @@ config ENTROPY_MCUX_TRNG
default y if HAS_MCUX_TRNG
depends on ENTROPY_GENERATOR
config ADC_MCUX_LPADC
default y if HAS_MCUX_LPADC
depends on ADC
#
# MBEDTLS is larger but much faster than TinyCrypt so choose wisely
#

1
soc/arm/nxp_imx/rt6xx/Kconfig.soc
View file

@ -21,6 +21,7 @@ config SOC_MIMXRT685S_CM33
select HAS_MCUX_FLEXSPI
select HAS_MCUX_CACHE
select HAS_MCUX_LPC_DMA
select HAS_MCUX_LPADC
select HAS_MCUX_OS_TIMER
select HAS_MCUX_LPC_RTC
select HAS_MCUX_TRNG

3
tests/drivers/adc/adc_api/src/test_adc.c
View file

@ -256,7 +256,8 @@
#elif defined(CONFIG_BOARD_LPCXPRESSO55S69_CPU0) || \
defined(CONFIG_BOARD_LPCXPRESSO55S28) || \
defined(CONFIG_BOARD_MIMXRT1170_EVK_CM7)
defined(CONFIG_BOARD_MIMXRT1170_EVK_CM7) || \
defined(CONFIG_BOARD_MIMXRT685_EVK)
#define ADC_DEVICE_NAME DT_LABEL(DT_INST(0, nxp_lpc_lpadc))
#define ADC_RESOLUTION 12
#define ADC_GAIN ADC_GAIN_1

2
west.yml
View file

@ -88,7 +88,7 @@ manifest:
groups:
- hal
- name: hal_nxp
revision: 6287a073922a42685cc0b63b97d35b49b66b7a8f
revision: 38e443d055afcdfe5306103d740ae10d4bf77e5b
path: modules/hal/nxp
groups:
- hal