diff --git a/drivers/dai/intel/dmic/dmic_nhlt.c b/drivers/dai/intel/dmic/dmic_nhlt.c
index c7fe48e1432..5f150e6d037 100644
--- a/drivers/dai/intel/dmic/dmic_nhlt.c
+++ b/drivers/dai/intel/dmic/dmic_nhlt.c
@@ -279,7 +279,7 @@ static int dai_nhlt_dmic_dai_params_get(struct dai_intel_dmic *dmic, const int c
 static inline void dai_dmic_clock_select_set(const struct dai_intel_dmic *dmic, uint32_t source)
 {
 	uint32_t val;
-#ifdef CONFIG_SOC_INTEL_ACE20_LNL /* Ace 2.0 */
+#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) /* ACE 2.0,3.0 */
 	val = sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET);
 	val &= ~DMICLVSCTL_MLCS;
 	val |= FIELD_PREP(DMICLVSCTL_MLCS, source);
@@ -300,7 +300,7 @@ static inline void dai_dmic_clock_select_set(const struct dai_intel_dmic *dmic,
 static inline uint32_t dai_dmic_clock_select_get(const struct dai_intel_dmic *dmic)
 {
 	uint32_t val;
-#ifdef CONFIG_SOC_INTEL_ACE20_LNL /* Ace 2.0 */
+#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) /* ACE 2.0,3.0 */
 	val = sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET);
 	return FIELD_GET(DMICLVSCTL_MLCS, val);
 #else
@@ -322,7 +322,7 @@ static int dai_dmic_set_clock(const struct dai_intel_dmic *dmic, const uint8_t c
 		return -ENOTSUP;
 	}
 
-#ifndef CONFIG_SOC_INTEL_ACE20_LNL /* Ace 2.0 */
+#if defined(CONFIG_SOC_INTEL_ACE15_MTPM)
 	if (clock_source && !(sys_read32(dmic->shim_base + DMICLCAP_OFFSET) & DMICLCAP_MLCS)) {
 		return -ENOTSUP;
 	}
diff --git a/soc/intel/intel_adsp/ace/include/ace30_ptl/dmic_regs_ace3x.h b/soc/intel/intel_adsp/ace/include/ace30_ptl/dmic_regs_ace3x.h
new file mode 100644
index 00000000000..4d02abea749
--- /dev/null
+++ b/soc/intel/intel_adsp/ace/include/ace30_ptl/dmic_regs_ace3x.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2024 Intel Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __INTEL_DAI_DRIVER_DMIC_REGS_ACE3X_H__
+#define __INTEL_DAI_DRIVER_DMIC_REGS_ACE3X_H__
+
+/* DMIC Link Synchronization */
+#define DMICSYNC_OFFSET		0x1C
+
+/* Sync Period */
+#define DMICSYNC_SYNCPRD	GENMASK(19, 0)
+
+/* Sync Period Update */
+#define DMICSYNC_SYNCPU		BIT(20)
+
+/* Sync Go */
+#define DMICSYNC_SYNCGO		BIT(23)
+
+/* Command Sync */
+#define DMICSYNC_CMDSYNC	BIT(24)
+
+
+/* DMIC Link Control */
+#define DMICLCTL_OFFSET		0x04
+
+/* Set Clock Frequency */
+#define DMICLCTL_SCF		GENMASK(3, 0)
+
+/* Offload Enable */
+#define DMICLCTL_OFLEN		BIT(4)
+
+/* Interrupt Enable */
+#define DMICLCTL_INTEN		BIT(5)
+
+/* Set Power Active */
+#define DMICLCTL_SPA		BIT(16)
+
+/* Current Power Active */
+#define DMICLCTL_CPA		BIT(23)
+
+/* Interrupt Status */
+#define DMICLCTL_INTSTS		BIT(31)
+
+
+/* Digital Microphone x Link Vendor Specific Control */
+#define DMICLVSCTL_OFFSET	0x04
+
+/* Force Clock Gating */
+#define DMICLVSCTL_FCG		BIT(26)
+
+/* Host Link Clock Select */
+#define DMICLVSCTL_MLCS		GENMASK(29, 27)
+
+/* Dynamic Clock Gating Disable */
+#define DMICLVSCTL_DCGD		BIT(30)
+
+/* Idle Clock Gating Disable */
+#define DMICLVSCTL_ICGD		BIT(31)
+
+
+/* Digital Microphone PCM Stream y Channel Map
+ *
+ * Offset: 12h + 02h * y
+ */
+#define DMICXPCMSyCM_OFFSET	0x16
+#define DMICXPCMSyCM_SIZE	0x02
+
+#endif /* !__INTEL_DAI_DRIVER_DMIC_REGS_ACE3X_H__ */
diff --git a/soc/intel/intel_adsp/ace/include/dmic_regs.h b/soc/intel/intel_adsp/ace/include/dmic_regs.h
index 201c3b2d6df..df69d3687f1 100644
--- a/soc/intel/intel_adsp/ace/include/dmic_regs.h
+++ b/soc/intel/intel_adsp/ace/include/dmic_regs.h
@@ -351,6 +351,8 @@
 #include <ace20_lnl/dmic_regs_ace2x.h>
 #elif CONFIG_SOC_INTEL_ACE15_MTPM
 #include <ace15_mtpm/dmic_regs_ace1x.h>
+#elif CONFIG_SOC_INTEL_ACE30_PTL
+#include <ace30_ptl/dmic_regs_ace3x.h>
 #else
 #error "Unknown SoC"
 #endif