From d33d5b3a7949e57e6bddb25f5fcf1f40a68e45d0 Mon Sep 17 00:00:00 2001
From: Sadik Ozer <sadik.ozer@analog.com>
Date: Fri, 13 Oct 2023 16:23:57 +0300
Subject: [PATCH] soc: Add the MAX32690 SoC

Added ADI MAX series soc, first partnumber is MAX32690
The family structure will be
ADI_MAX
  MAX32xxx
    MAX32655
      MAX32655EVKIT
      MAX32655FTHR
    MAX32666
      MAX32666FTHR
      MAX32666FTHR2
    MAX32690
      MAX32690EVKIT
  MAX78xxx
    MAX78000
    MAX78002
        ...

When MAX32 MCUs goes to sleep mode debugger could not access it
and flashing fails, ARM_ON_ENTER_CPU_IDLE_HOOK prevent
the CPU from actually entering sleep
by skipping the WFE/WFI instruction.
Due to ARM_ON_ENTER_CPU_IDLE_HOOK is not configurable at the user
space, added a config wrapper as MAX32_ON_ENTER_CPU_IDLE_HOOK.

If MAX32_ON_ENTER_CPU_IDLE_HOOK config being defined (default y)
devicei will not goes to sleep mode in idle state.

To disable it add below line in your configuration file
CONFIG_MAX32_ON_ENTER_CPU_IDLE_HOOK=n

MAX32690 has two core Cortex-M4 and Risc-V this commit adds M4 core
support.

Co-authored-by: Jason Murphy <jason.murphy@analog.com>
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
---
 dts/arm/adi/max32/max32690-pinctrl.dtsi  | 771 +++++++++++++++++++++++
 dts/arm/adi/max32/max32690.dtsi          | 123 ++++
 dts/arm/adi/max32/max32xxx.dtsi          | 162 +++++
 soc/adi/max32/CMakeLists.txt             |   8 +
 soc/adi/max32/Kconfig                    |  29 +
 soc/adi/max32/Kconfig.defconfig          |  13 +
 soc/adi/max32/Kconfig.defconfig.max32690 |  14 +
 soc/adi/max32/Kconfig.soc                |  21 +
 soc/adi/max32/soc.c                      |  41 ++
 soc/adi/max32/soc.h                      |  17 +
 soc/adi/max32/soc.yml                    |   9 +
 11 files changed, 1208 insertions(+)
 create mode 100644 dts/arm/adi/max32/max32690-pinctrl.dtsi
 create mode 100644 dts/arm/adi/max32/max32690.dtsi
 create mode 100644 dts/arm/adi/max32/max32xxx.dtsi
 create mode 100644 soc/adi/max32/CMakeLists.txt
 create mode 100644 soc/adi/max32/Kconfig
 create mode 100644 soc/adi/max32/Kconfig.defconfig
 create mode 100644 soc/adi/max32/Kconfig.defconfig.max32690
 create mode 100644 soc/adi/max32/Kconfig.soc
 create mode 100644 soc/adi/max32/soc.c
 create mode 100644 soc/adi/max32/soc.h
 create mode 100644 soc/adi/max32/soc.yml

diff --git a/dts/arm/adi/max32/max32690-pinctrl.dtsi b/dts/arm/adi/max32/max32690-pinctrl.dtsi
new file mode 100644
index 00000000000..18fab74ba2f
--- /dev/null
+++ b/dts/arm/adi/max32/max32690-pinctrl.dtsi
@@ -0,0 +1,771 @@
+/*
+ * Copyright (c) 2023-2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/max32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@40008000 {
+
+			/omit-if-no-ref/ spixr_sdio0_p0_1: spixr_sdio0_p0_1 {
+				pinmux = <MAX32_PINMUX(0, 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ spixf_sdio0_p0_1: spixf_sdio0_p0_1 {
+				pinmux = <MAX32_PINMUX(0, 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart2c_tx_p0_1: uart2c_tx_p0_1 {
+				pinmux = <MAX32_PINMUX(0, 1, AF3)>;
+			};
+
+			/omit-if-no-ref/ spixr_sdio2_p0_2: spixr_sdio2_p0_2 {
+				pinmux = <MAX32_PINMUX(0, 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ spixf_sdio2_p0_2: spixf_sdio2_p0_2 {
+				pinmux = <MAX32_PINMUX(0, 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart2c_cts_p0_2: uart2c_cts_p0_2 {
+				pinmux = <MAX32_PINMUX(0, 2, AF3)>;
+			};
+
+			/omit-if-no-ref/ spixr_sck_p0_3: spixr_sck_p0_3 {
+				pinmux = <MAX32_PINMUX(0, 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ spixf_sck_p0_3: spixf_sck_p0_3 {
+				pinmux = <MAX32_PINMUX(0, 3, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart2c_rts_p0_3: uart2c_rts_p0_3 {
+				pinmux = <MAX32_PINMUX(0, 3, AF3)>;
+			};
+
+			/omit-if-no-ref/ spixr_sdio3_p0_4: spixr_sdio3_p0_4 {
+				pinmux = <MAX32_PINMUX(0, 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ spixf_sdio3_p0_4: spixf_sdio3_p0_4 {
+				pinmux = <MAX32_PINMUX(0, 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr0c_ioa_p0_4: tmr0c_ioa_p0_4 {
+				pinmux = <MAX32_PINMUX(0, 4, AF3)>;
+			};
+
+			/omit-if-no-ref/ spixr_sdio1_p0_5: spixr_sdio1_p0_5 {
+				pinmux = <MAX32_PINMUX(0, 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ spixf_sdio1_p0_5: spixf_sdio1_p0_5 {
+				pinmux = <MAX32_PINMUX(0, 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr2c_iob_p0_5: tmr2c_iob_p0_5 {
+				pinmux = <MAX32_PINMUX(0, 5, AF3)>;
+			};
+
+			/omit-if-no-ref/ spixr_ss0_p0_6: spixr_ss0_p0_6 {
+				pinmux = <MAX32_PINMUX(0, 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ spixf_ss0_p0_6: spixf_ss0_p0_6 {
+				pinmux = <MAX32_PINMUX(0, 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart2c_rx_p0_6: uart2c_rx_p0_6 {
+				pinmux = <MAX32_PINMUX(0, 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ owm_pe_p0_7: owm_pe_p0_7 {
+				pinmux = <MAX32_PINMUX(0, 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr1b_ioa_p0_7: tmr1b_ioa_p0_7 {
+				pinmux = <MAX32_PINMUX(0, 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ owm_io_p0_8: owm_io_p0_8 {
+				pinmux = <MAX32_PINMUX(0, 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr1b_iob_p0_8: tmr1b_iob_p0_8 {
+				pinmux = <MAX32_PINMUX(0, 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ adc_clk_ext_p0_9: adc_clk_ext_p0_9 {
+				pinmux = <MAX32_PINMUX(0, 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr0c_ioan_p0_9: tmr0c_ioan_p0_9 {
+				pinmux = <MAX32_PINMUX(0, 9, AF3)>;
+			};
+
+			/omit-if-no-ref/ adc_trig_a_p0_10: adc_trig_a_p0_10 {
+				pinmux = <MAX32_PINMUX(0, 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr0c_iobn_p0_10: tmr0c_iobn_p0_10 {
+				pinmux = <MAX32_PINMUX(0, 10, AF3)>;
+			};
+
+			/omit-if-no-ref/ i2c1a_sda_p0_11: i2c1a_sda_p0_11 {
+				pinmux = <MAX32_PINMUX(0, 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr1c_ioan_p0_11: tmr1c_ioan_p0_11 {
+				pinmux = <MAX32_PINMUX(0, 11, AF3)>;
+			};
+
+			/omit-if-no-ref/ i2c1a_scl_p0_12: i2c1a_scl_p0_12 {
+				pinmux = <MAX32_PINMUX(0, 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr1c_iobn_p0_12: tmr1c_iobn_p0_12 {
+				pinmux = <MAX32_PINMUX(0, 12, AF3)>;
+			};
+
+			/omit-if-no-ref/ spi3a_ss1_p0_13: spi3a_ss1_p0_13 {
+				pinmux = <MAX32_PINMUX(0, 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr0b_ioa_p0_13: tmr0b_ioa_p0_13 {
+				pinmux = <MAX32_PINMUX(0, 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2c2c_sda_p0_13: i2c2c_sda_p0_13 {
+				pinmux = <MAX32_PINMUX(0, 13, AF3)>;
+			};
+
+			/omit-if-no-ref/ spi3a_ss2_p0_14: spi3a_ss2_p0_14 {
+				pinmux = <MAX32_PINMUX(0, 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr0b_iob_p0_14: tmr0b_iob_p0_14 {
+				pinmux = <MAX32_PINMUX(0, 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2c2c_scl_p0_14: i2c2c_scl_p0_14 {
+				pinmux = <MAX32_PINMUX(0, 14, AF3)>;
+			};
+
+			/omit-if-no-ref/ spi3a_sdio3_p0_15: spi3a_sdio3_p0_15 {
+				pinmux = <MAX32_PINMUX(0, 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr1c_ioa_p0_15: tmr1c_ioa_p0_15 {
+				pinmux = <MAX32_PINMUX(0, 15, AF3)>;
+			};
+
+			/omit-if-no-ref/ spi3a_sck_p0_16: spi3a_sck_p0_16 {
+				pinmux = <MAX32_PINMUX(0, 16, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi3a_sdio2_p0_17: spi3a_sdio2_p0_17 {
+				pinmux = <MAX32_PINMUX(0, 17, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr1c_iob_p0_17: tmr1c_iob_p0_17 {
+				pinmux = <MAX32_PINMUX(0, 17, AF3)>;
+			};
+
+			/omit-if-no-ref/ spi3a_ss0_p0_19: spi3a_ss0_p0_19 {
+				pinmux = <MAX32_PINMUX(0, 19, AF1)>;
+			};
+
+			/omit-if-no-ref/ rv_tck_p0_19: rv_tck_p0_19 {
+				pinmux = <MAX32_PINMUX(0, 19, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi3a_miso_p0_20: spi3a_miso_p0_20 {
+				pinmux = <MAX32_PINMUX(0, 20, AF1)>;
+			};
+
+			/omit-if-no-ref/ rv_tms_p0_20: rv_tms_p0_20 {
+				pinmux = <MAX32_PINMUX(0, 20, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi3a_mosi_p0_21: spi3a_mosi_p0_21 {
+				pinmux = <MAX32_PINMUX(0, 21, AF1)>;
+			};
+
+			/omit-if-no-ref/ rv_tdi_p0_21: rv_tdi_p0_21 {
+				pinmux = <MAX32_PINMUX(0, 21, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi0a_ss0_p0_22: spi0a_ss0_p0_22 {
+				pinmux = <MAX32_PINMUX(0, 22, AF1)>;
+			};
+
+			/omit-if-no-ref/ rv_tdo_p0_22: rv_tdo_p0_22 {
+				pinmux = <MAX32_PINMUX(0, 22, AF2)>;
+			};
+
+			/omit-if-no-ref/ pt15_p0_23: pt15_p0_23 {
+				pinmux = <MAX32_PINMUX(0, 23, AF1)>;
+			};
+
+			/omit-if-no-ref/ i2s0b_clkext_p0_23: i2s0b_clkext_p0_23 {
+				pinmux = <MAX32_PINMUX(0, 23, AF2)>;
+			};
+
+			/omit-if-no-ref/ rxev0_p0_24: rxev0_p0_24 {
+				pinmux = <MAX32_PINMUX(0, 24, AF1)>;
+			};
+
+			/omit-if-no-ref/ i2s0b_sck_p0_24: i2s0b_sck_p0_24 {
+				pinmux = <MAX32_PINMUX(0, 24, AF2)>;
+			};
+
+			/omit-if-no-ref/ txevo_p0_25: txevo_p0_25 {
+				pinmux = <MAX32_PINMUX(0, 25, AF1)>;
+			};
+
+			/omit-if-no-ref/ i2s0b_sdi_p0_25: i2s0b_sdi_p0_25 {
+				pinmux = <MAX32_PINMUX(0, 25, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2s0b_sdo_p0_26: i2s0b_sdo_p0_26 {
+				pinmux = <MAX32_PINMUX(0, 26, AF2)>;
+			};
+
+			/omit-if-no-ref/ erfo_clk_out_p0_27: erfo_clk_out_p0_27 {
+				pinmux = <MAX32_PINMUX(0, 27, AF1)>;
+			};
+
+			/omit-if-no-ref/ i2s0b_ws_p0_27: i2s0b_ws_p0_27 {
+				pinmux = <MAX32_PINMUX(0, 27, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2c0a_sda_p0_30: i2c0a_sda_p0_30 {
+				pinmux = <MAX32_PINMUX(0, 30, AF1)>;
+			};
+
+			/omit-if-no-ref/ i2c0a_scl_p0_31: i2c0a_scl_p0_31 {
+				pinmux = <MAX32_PINMUX(0, 31, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi4a_ss0_p1_0: spi4a_ss0_p1_0 {
+				pinmux = <MAX32_PINMUX(1, 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ adc_trig_b_p1_0: adc_trig_b_p1_0 {
+				pinmux = <MAX32_PINMUX(1, 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi4a_mosi_p1_1: spi4a_mosi_p1_1 {
+				pinmux = <MAX32_PINMUX(1, 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi4a_miso_p1_2: spi4a_miso_p1_2 {
+				pinmux = <MAX32_PINMUX(1, 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi4a_sck_p1_3: spi4a_sck_p1_3 {
+				pinmux = <MAX32_PINMUX(1, 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi4a_sdio2_p1_4: spi4a_sdio2_p1_4 {
+				pinmux = <MAX32_PINMUX(1, 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr2b_ioa_p1_4: tmr2b_ioa_p1_4 {
+				pinmux = <MAX32_PINMUX(1, 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi4a_sdio3_p1_5: spi4a_sdio3_p1_5 {
+				pinmux = <MAX32_PINMUX(1, 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr2b_iob_p1_5: tmr2b_iob_p1_5 {
+				pinmux = <MAX32_PINMUX(1, 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi4a_ss1_p1_6: spi4a_ss1_p1_6 {
+				pinmux = <MAX32_PINMUX(1, 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt0_p1_6: pt0_p1_6 {
+				pinmux = <MAX32_PINMUX(1, 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart2a_cts_p1_7: uart2a_cts_p1_7 {
+				pinmux = <MAX32_PINMUX(1, 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt1_p1_7: pt1_p1_7 {
+				pinmux = <MAX32_PINMUX(1, 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2c2c_sda_p1_7: i2c2c_sda_p1_7 {
+				pinmux = <MAX32_PINMUX(1, 7, AF3)>;
+			};
+
+			/omit-if-no-ref/ uart2a_rts_p1_8: uart2a_rts_p1_8 {
+				pinmux = <MAX32_PINMUX(1, 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt2_p1_8: pt2_p1_8 {
+				pinmux = <MAX32_PINMUX(1, 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2c2c_scl_p1_8: i2c2c_scl_p1_8 {
+				pinmux = <MAX32_PINMUX(1, 8, AF3)>;
+			};
+
+			/omit-if-no-ref/ uart2a_rx_p1_9: uart2a_rx_p1_9 {
+				pinmux = <MAX32_PINMUX(1, 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt3_p1_9: pt3_p1_9 {
+				pinmux = <MAX32_PINMUX(1, 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart2a_tx_p1_10: uart2a_tx_p1_10 {
+				pinmux = <MAX32_PINMUX(1, 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt4_p1_10: pt4_p1_10 {
+				pinmux = <MAX32_PINMUX(1, 10, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi4a_ss2_p1_11: spi4a_ss2_p1_11 {
+				pinmux = <MAX32_PINMUX(1, 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ hyp_cs0n_p1_11: hyp_cs0n_p1_11 {
+				pinmux = <MAX32_PINMUX(1, 11, AF3)>;
+			};
+
+			/omit-if-no-ref/ pt5_p1_12: pt5_p1_12 {
+				pinmux = <MAX32_PINMUX(1, 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ hyp_d0_p1_12: hyp_d0_p1_12 {
+				pinmux = <MAX32_PINMUX(1, 12, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr3a_ioa_p1_13: tmr3a_ioa_p1_13 {
+				pinmux = <MAX32_PINMUX(1, 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ hyp_d4_p1_13: hyp_d4_p1_13 {
+				pinmux = <MAX32_PINMUX(1, 13, AF3)>;
+			};
+
+			/omit-if-no-ref/ tmr3a_iob_p1_14: tmr3a_iob_p1_14 {
+				pinmux = <MAX32_PINMUX(1, 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ hyp_rwds_p1_14: hyp_rwds_p1_14 {
+				pinmux = <MAX32_PINMUX(1, 14, AF3)>;
+			};
+
+			/omit-if-no-ref/ hyp_d1_p1_15: hyp_d1_p1_15 {
+				pinmux = <MAX32_PINMUX(1, 15, AF3)>;
+			};
+
+			/omit-if-no-ref/ hyp_d5_p1_16: hyp_d5_p1_16 {
+				pinmux = <MAX32_PINMUX(1, 16, AF3)>;
+			};
+
+			/omit-if-no-ref/ pt9_p1_17: pt9_p1_17 {
+				pinmux = <MAX32_PINMUX(1, 17, AF1)>;
+			};
+
+			/omit-if-no-ref/ hyp_cs1n_p1_17: hyp_cs1n_p1_17 {
+				pinmux = <MAX32_PINMUX(1, 17, AF3)>;
+			};
+
+			/omit-if-no-ref/ pt6_p1_18: pt6_p1_18 {
+				pinmux = <MAX32_PINMUX(1, 18, AF2)>;
+			};
+
+			/omit-if-no-ref/ hyp_d6_p1_18: hyp_d6_p1_18 {
+				pinmux = <MAX32_PINMUX(1, 18, AF3)>;
+			};
+
+			/omit-if-no-ref/ pt7_p1_19: pt7_p1_19 {
+				pinmux = <MAX32_PINMUX(1, 19, AF2)>;
+			};
+
+			/omit-if-no-ref/ hyp_d2_p1_19: hyp_d2_p1_19 {
+				pinmux = <MAX32_PINMUX(1, 19, AF3)>;
+			};
+
+			/omit-if-no-ref/ hyp_d3_p1_20: hyp_d3_p1_20 {
+				pinmux = <MAX32_PINMUX(1, 20, AF3)>;
+			};
+
+			/omit-if-no-ref/ pt8_p1_21: pt8_p1_21 {
+				pinmux = <MAX32_PINMUX(1, 21, AF2)>;
+			};
+
+			/omit-if-no-ref/ hyp_d7_p1_21: hyp_d7_p1_21 {
+				pinmux = <MAX32_PINMUX(1, 21, AF3)>;
+			};
+
+			/omit-if-no-ref/ spi1a_ss0_p1_23: spi1a_ss0_p1_23 {
+				pinmux = <MAX32_PINMUX(1, 23, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi1a_ss2_p1_24: spi1a_ss2_p1_24 {
+				pinmux = <MAX32_PINMUX(1, 24, AF1)>;
+			};
+
+			/omit-if-no-ref/ can0b_rx_p1_24: can0b_rx_p1_24 {
+				pinmux = <MAX32_PINMUX(1, 24, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi1a_ss1_p1_25: spi1a_ss1_p1_25 {
+				pinmux = <MAX32_PINMUX(1, 25, AF1)>;
+			};
+
+			/omit-if-no-ref/ can0b_tx_p1_25: can0b_tx_p1_25 {
+				pinmux = <MAX32_PINMUX(1, 25, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi1a_sck_p1_26: spi1a_sck_p1_26 {
+				pinmux = <MAX32_PINMUX(1, 26, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi2a_ss2_p1_27: spi2a_ss2_p1_27 {
+				pinmux = <MAX32_PINMUX(1, 27, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi1a_miso_p1_28: spi1a_miso_p1_28 {
+				pinmux = <MAX32_PINMUX(1, 28, AF1)>;
+			};
+
+			/omit-if-no-ref/ can1b_rx_p1_28: can1b_rx_p1_28 {
+				pinmux = <MAX32_PINMUX(1, 28, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi1a_mosi_p1_29: spi1a_mosi_p1_29 {
+				pinmux = <MAX32_PINMUX(1, 29, AF1)>;
+			};
+
+			/omit-if-no-ref/ can1b_tx_p1_29: can1b_tx_p1_29 {
+				pinmux = <MAX32_PINMUX(1, 29, AF2)>;
+			};
+
+			/omit-if-no-ref/ owm_pe_p1_30: owm_pe_p1_30 {
+				pinmux = <MAX32_PINMUX(1, 30, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi1b_sdio2_p1_30: spi1b_sdio2_p1_30 {
+				pinmux = <MAX32_PINMUX(1, 30, AF2)>;
+			};
+
+			/omit-if-no-ref/ owm_io_p1_31: owm_io_p1_31 {
+				pinmux = <MAX32_PINMUX(1, 31, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi1b_sdio3_p1_31: spi1b_sdio3_p1_31 {
+				pinmux = <MAX32_PINMUX(1, 31, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi2a_ss1_p2_1: spi2a_ss1_p2_1 {
+				pinmux = <MAX32_PINMUX(2, 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt10_p2_1: pt10_p2_1 {
+				pinmux = <MAX32_PINMUX(2, 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi2a_sck_p2_2: spi2a_sck_p2_2 {
+				pinmux = <MAX32_PINMUX(2, 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi2a_miso_p2_3: spi2a_miso_p2_3 {
+				pinmux = <MAX32_PINMUX(2, 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi2a_mosi_p2_4: spi2a_mosi_p2_4 {
+				pinmux = <MAX32_PINMUX(2, 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi2a_ss0_p2_5: spi2a_ss0_p2_5 {
+				pinmux = <MAX32_PINMUX(2, 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt11_p2_5: pt11_p2_5 {
+				pinmux = <MAX32_PINMUX(2, 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi2b_sdio2_p2_6: spi2b_sdio2_p2_6 {
+				pinmux = <MAX32_PINMUX(2, 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2c0a_sda_p2_7: i2c0a_sda_p2_7 {
+				pinmux = <MAX32_PINMUX(2, 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi2b_sdio3_p2_7: spi2b_sdio3_p2_7 {
+				pinmux = <MAX32_PINMUX(2, 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2c0a_scl_p2_8: i2c0a_scl_p2_8 {
+				pinmux = <MAX32_PINMUX(2, 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart0a_cts_p2_9: uart0a_cts_p2_9 {
+				pinmux = <MAX32_PINMUX(2, 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt12_p2_9: pt12_p2_9 {
+				pinmux = <MAX32_PINMUX(2, 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart0a_rts_p2_10: uart0a_rts_p2_10 {
+				pinmux = <MAX32_PINMUX(2, 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt14_p2_10: pt14_p2_10 {
+				pinmux = <MAX32_PINMUX(2, 10, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart0a_rx_p2_11: uart0a_rx_p2_11 {
+				pinmux = <MAX32_PINMUX(2, 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt13_p2_11: pt13_p2_11 {
+				pinmux = <MAX32_PINMUX(2, 11, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart0a_tx_p2_12: uart0a_tx_p2_12 {
+				pinmux = <MAX32_PINMUX(2, 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt15_p2_12: pt15_p2_12 {
+				pinmux = <MAX32_PINMUX(2, 12, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart1a_cts_p2_13: uart1a_cts_p2_13 {
+				pinmux = <MAX32_PINMUX(2, 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart1a_rx_p2_14: uart1a_rx_p2_14 {
+				pinmux = <MAX32_PINMUX(2, 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart1a_rts_p2_15: uart1a_rts_p2_15 {
+				pinmux = <MAX32_PINMUX(2, 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ adc_hw_trig_c_p2_15: adc_hw_trig_c_p2_15 {
+				pinmux = <MAX32_PINMUX(2, 15, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart1a_tx_p2_16: uart1a_tx_p2_16 {
+				pinmux = <MAX32_PINMUX(2, 16, AF1)>;
+			};
+
+			/omit-if-no-ref/ i2c1a_sda_p2_17: i2c1a_sda_p2_17 {
+				pinmux = <MAX32_PINMUX(2, 17, AF1)>;
+			};
+
+			/omit-if-no-ref/ ble_ant_ctrl1_p2_17: ble_ant_ctrl1_p2_17 {
+				pinmux = <MAX32_PINMUX(2, 17, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2c1a_scl_p2_18: i2c1a_scl_p2_18 {
+				pinmux = <MAX32_PINMUX(2, 18, AF1)>;
+			};
+
+			/omit-if-no-ref/ ble_ant_ctrl0_p2_18: ble_ant_ctrl0_p2_18 {
+				pinmux = <MAX32_PINMUX(2, 18, AF2)>;
+			};
+
+			/omit-if-no-ref/ pt5_p2_20: pt5_p2_20 {
+				pinmux = <MAX32_PINMUX(2, 20, AF1)>;
+			};
+
+			/omit-if-no-ref/ ble_ant_ctrl2_p2_20: ble_ant_ctrl2_p2_20 {
+				pinmux = <MAX32_PINMUX(2, 20, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr2c_ioa_p2_20: tmr2c_ioa_p2_20 {
+				pinmux = <MAX32_PINMUX(2, 20, AF3)>;
+			};
+
+			/omit-if-no-ref/ pt7_p2_21: pt7_p2_21 {
+				pinmux = <MAX32_PINMUX(2, 21, AF1)>;
+			};
+
+			/omit-if-no-ref/ ble_ant_ctrl3_p2_21: ble_ant_ctrl3_p2_21 {
+				pinmux = <MAX32_PINMUX(2, 21, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr2c_iob_p2_21: tmr2c_iob_p2_21 {
+				pinmux = <MAX32_PINMUX(2, 21, AF3)>;
+			};
+
+			/omit-if-no-ref/ pt8_p2_22: pt8_p2_22 {
+				pinmux = <MAX32_PINMUX(2, 22, AF1)>;
+			};
+
+			/omit-if-no-ref/ can0b_rx_p2_22: can0b_rx_p2_22 {
+				pinmux = <MAX32_PINMUX(2, 22, AF2)>;
+			};
+
+			/omit-if-no-ref/ pt6_p2_23: pt6_p2_23 {
+				pinmux = <MAX32_PINMUX(2, 23, AF1)>;
+			};
+
+			/omit-if-no-ref/ can0b_tx_p2_23: can0b_tx_p2_23 {
+				pinmux = <MAX32_PINMUX(2, 23, AF2)>;
+			};
+
+			/omit-if-no-ref/ pt10_p2_24: pt10_p2_24 {
+				pinmux = <MAX32_PINMUX(2, 24, AF1)>;
+			};
+
+			/omit-if-no-ref/ can1b_rx_p2_24: can1b_rx_p2_24 {
+				pinmux = <MAX32_PINMUX(2, 24, AF2)>;
+			};
+
+			/omit-if-no-ref/ pt11_p2_25: pt11_p2_25 {
+				pinmux = <MAX32_PINMUX(2, 25, AF1)>;
+			};
+
+			/omit-if-no-ref/ can1b_tx_p2_25: can1b_tx_p2_25 {
+				pinmux = <MAX32_PINMUX(2, 25, AF2)>;
+			};
+
+			/omit-if-no-ref/ pt12_p2_26: pt12_p2_26 {
+				pinmux = <MAX32_PINMUX(2, 26, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi0b_ss1_p2_26: spi0b_ss1_p2_26 {
+				pinmux = <MAX32_PINMUX(2, 26, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2s0c_ws_p2_26: i2s0c_ws_p2_26 {
+				pinmux = <MAX32_PINMUX(2, 26, AF3)>;
+			};
+
+			/omit-if-no-ref/ pt13_p2_27: pt13_p2_27 {
+				pinmux = <MAX32_PINMUX(2, 27, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi0b_miso_p2_27: spi0b_miso_p2_27 {
+				pinmux = <MAX32_PINMUX(2, 27, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2s0c_sdi_p2_27: i2s0c_sdi_p2_27 {
+				pinmux = <MAX32_PINMUX(2, 27, AF3)>;
+			};
+
+			/omit-if-no-ref/ pt14_p2_28: pt14_p2_28 {
+				pinmux = <MAX32_PINMUX(2, 28, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi0b_mosi_p2_28: spi0b_mosi_p2_28 {
+				pinmux = <MAX32_PINMUX(2, 28, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2s0c_sdo_p2_28: i2s0c_sdo_p2_28 {
+				pinmux = <MAX32_PINMUX(2, 28, AF3)>;
+			};
+
+			/omit-if-no-ref/ pt0_p2_29: pt0_p2_29 {
+				pinmux = <MAX32_PINMUX(2, 29, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi0b_sck_p2_29: spi0b_sck_p2_29 {
+				pinmux = <MAX32_PINMUX(2, 29, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2s0c_sck_p2_29: i2s0c_sck_p2_29 {
+				pinmux = <MAX32_PINMUX(2, 29, AF3)>;
+			};
+
+			/omit-if-no-ref/ pt1_p2_30: pt1_p2_30 {
+				pinmux = <MAX32_PINMUX(2, 30, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi0b_sdio2_p2_30: spi0b_sdio2_p2_30 {
+				pinmux = <MAX32_PINMUX(2, 30, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr3c_ioa_p2_30: tmr3c_ioa_p2_30 {
+				pinmux = <MAX32_PINMUX(2, 30, AF3)>;
+			};
+
+			/omit-if-no-ref/ pt2_p2_31: pt2_p2_31 {
+				pinmux = <MAX32_PINMUX(2, 31, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi0b_sdio3_p2_31: spi0b_sdio3_p2_31 {
+				pinmux = <MAX32_PINMUX(2, 31, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr3c_iob_p2_31: tmr3c_iob_p2_31 {
+				pinmux = <MAX32_PINMUX(2, 31, AF3)>;
+			};
+
+			/omit-if-no-ref/ ain0_p3_0: ain0_p3_0 {
+				pinmux = <MAX32_PINMUX(3, 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ lpuart0b_rx_p3_0: lpuart0b_rx_p3_0 {
+				pinmux = <MAX32_PINMUX(3, 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ ain1_p3_1: ain1_p3_1 {
+				pinmux = <MAX32_PINMUX(3, 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ lpuart0b_tx_p3_1: lpuart0b_tx_p3_1 {
+				pinmux = <MAX32_PINMUX(3, 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ ain2_p3_2: ain2_p3_2 {
+				pinmux = <MAX32_PINMUX(3, 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ lpuart0b_cts_p3_2: lpuart0b_cts_p3_2 {
+				pinmux = <MAX32_PINMUX(3, 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ ain3_p3_3: ain3_p3_3 {
+				pinmux = <MAX32_PINMUX(3, 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ lpuart0b_rts_p3_3: lpuart0b_rts_p3_3 {
+				pinmux = <MAX32_PINMUX(3, 3, AF2)>;
+			};
+
+			/omit-if-no-ref/ ain4_p3_4: ain4_p3_4 {
+				pinmux = <MAX32_PINMUX(3, 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ lptmr0b_ioa_p3_4: lptmr0b_ioa_p3_4 {
+				pinmux = <MAX32_PINMUX(3, 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ ain5_p3_5: ain5_p3_5 {
+				pinmux = <MAX32_PINMUX(3, 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ ain6_p3_6: ain6_p3_6 {
+				pinmux = <MAX32_PINMUX(3, 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ ain7_p3_7: ain7_p3_7 {
+				pinmux = <MAX32_PINMUX(3, 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ lptmr1b_ioa_p3_7: lptmr1b_ioa_p3_7 {
+				pinmux = <MAX32_PINMUX(3, 7, AF2)>;
+			};
+
+		};
+	};
+};
diff --git a/dts/arm/adi/max32/max32690.dtsi b/dts/arm/adi/max32/max32690.dtsi
new file mode 100644
index 00000000000..2bfef0e4be3
--- /dev/null
+++ b/dts/arm/adi/max32/max32690.dtsi
@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2023-2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+#include <adi/max32/max32xxx.dtsi>
+
+&clk_ipo {
+	clock-frequency = <DT_FREQ_M(120)>;
+};
+
+&sram0 {
+	reg = <0x20000000 DT_SIZE_K(128)>;
+};
+
+&flash0 {
+	reg = <0x10000000 DT_SIZE_M(3)>;
+	erase-block-size = <16384>;
+};
+
+&gcr {
+	/delete-property/ sysclk-prescaler;
+};
+
+&pinctrl {
+	reg = <0x40008000 0x3220>;
+
+	gpio2: gpio@4000a000 {
+		reg = <0x4000a000 0x1000>;
+		compatible = "adi,max32-gpio";
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupts = <26 0>;
+		clocks = <&gcr ADI_MAX32_CLOCK_BUS0 2>;
+		status = "disabled";
+	};
+
+	gpio3: gpio@40080400 {
+		reg = <0x40080400 0x200>;
+		compatible = "adi,max32-gpio";
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupts = <58 0>;
+		clocks = <&gcr ADI_MAX32_CLOCK_BUS2 0>;
+		status = "disabled";
+	};
+
+	gpio4: gpio@4000c000 {
+		reg = <0x4000c000 0x20>;
+		compatible = "adi,max32-gpio";
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupts = <54 0>;
+		status = "disabled";
+	};
+};
+
+/* MAX32690 extra peripherals. */
+/ {
+	soc {
+		sram1: memory@20020000 {
+			compatible = "mmio-sram";
+			reg = <0x20020000 DT_SIZE_K(128)>;
+		};
+
+		sram2: memory@20040000 {
+			compatible = "mmio-sram";
+			reg = <0x20040000 DT_SIZE_K(128)>;
+		};
+
+		sram3: memory@20060000 {
+			compatible = "mmio-sram";
+			reg = <0x20060000 DT_SIZE_K(128)>;
+		};
+
+		sram4: memory@20080000 {
+			compatible = "mmio-sram";
+			reg = <0x20080000 DT_SIZE_K(128)>;
+		};
+
+		sram5: memory@200a0000 {
+			compatible = "mmio-sram";
+			reg = <0x200a0000 DT_SIZE_K(128)>;
+		};
+
+		sram6: memory@200c0000 {
+			compatible = "mmio-sram";
+			reg = <0x200c0000 DT_SIZE_K(64)>;
+		};
+
+		sram7: memory@200d0000 {
+			compatible = "mmio-sram";
+			reg = <0x200d0000 DT_SIZE_K(64)>;
+		};
+
+		flc1: flash_controller@40029400 {
+			compatible = "adi,max32-flash-controller";
+			reg = <0x40029400 0x400>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+			status = "okay";
+
+			flash1: flash@10080000 {
+				compatible = "soc-nv-flash";
+				reg = <0x10080000 DT_SIZE_K(256)>;
+				write-block-size = <16>;
+				erase-block-size = <16384>;
+			};
+		};
+
+		uart3: serial@40081400 {
+			compatible = "adi,max32-uart";
+			reg = <0x40081400 0x400>;
+			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 4>;
+			clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
+			interrupts = <88 0>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/dts/arm/adi/max32/max32xxx.dtsi b/dts/arm/adi/max32/max32xxx.dtsi
new file mode 100644
index 00000000000..64db7032960
--- /dev/null
+++ b/dts/arm/adi/max32/max32xxx.dtsi
@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2023-2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/clock/adi_max32_clock.h>
+
+#include <freq.h>
+
+/ {
+	chosen {
+		zephyr,flash-controller = &flc0;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m4f";
+			reg = <0>;
+		};
+	};
+
+	clocks {
+		clk_ipo: clk_ipo {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <DT_FREQ_M(100)>;
+			status = "disabled";
+		};
+
+		clk_iso: clk_iso {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <DT_FREQ_M(60)>;
+			status = "disabled";
+		};
+
+		clk_inro: clk_inro {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <DT_FREQ_K(8)>;
+			status = "disabled";
+		};
+
+		clk_ibro: clk_ibro {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <7372800>;
+			status = "disabled";
+		};
+
+		clk_ertco: clk_ertco {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32768>;
+			status = "disabled";
+		};
+
+		clk_erfo: clk_erfo {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <DT_FREQ_M(32)>;
+			status = "disabled";
+		};
+	};
+
+	soc {
+		sram0: memory@20000000 {
+			compatible = "mmio-sram";
+			reg = <0x20000000 DT_SIZE_K(32)>;
+		};
+
+		flc0: flash_controller@40029000 {
+			compatible = "flash-controller";
+			reg = <0x40029000 0x400>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+			status = "okay";
+
+			flash0: flash@10000000 {
+				compatible = "soc-nv-flash";
+				reg = <0x10000000 DT_SIZE_K(512)>;
+				write-block-size = <16>;
+				erase-block-size = <8192>;
+			};
+		};
+
+		gcr: clock-controller@40000000 {
+			reg = <0x40000000 0x400>;
+			compatible = "adi,max32-gcr";
+			#clock-cells = <2>;
+			clocks = <&clk_ipo>;
+			sysclk-prescaler = <1>;
+			status = "okay";
+		};
+
+		pinctrl: pin-controller@40008000 {
+			compatible = "adi,max32-pinctrl";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x40008000 0x2000>;
+
+			gpio0: gpio@40008000 {
+				reg = <0x40008000 0x1000>;
+				compatible = "adi,max32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&gcr ADI_MAX32_CLOCK_BUS0 0>;
+				interrupts = <24 0>;
+				status = "disabled";
+			};
+
+			gpio1: gpio@40009000 {
+				reg = <0x40009000 0x1000>;
+				compatible = "adi,max32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupts = <25 0>;
+				clocks = <&gcr ADI_MAX32_CLOCK_BUS0 1>;
+				status = "disabled";
+			};
+		};
+
+		uart0: serial@40042000 {
+			compatible = "adi,max32-uart";
+			reg = <0x40042000 0x1000>;
+			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 9>;
+			clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
+			interrupts = <14 0>;
+			status = "disabled";
+		};
+
+		uart1: serial@40043000 {
+			compatible = "adi,max32-uart";
+			reg = <0x40043000 0x1000>;
+			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 10>;
+			clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
+			interrupts = <15 0>;
+			status = "disabled";
+		};
+
+		uart2: serial@40044000 {
+			compatible = "adi,max32-uart";
+			reg = <0x40044000 0x1000>;
+			clocks = <&gcr ADI_MAX32_CLOCK_BUS1 1>;
+			clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
+			interrupts = <34 0>;
+			status = "disabled";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <3>;
+};
diff --git a/soc/adi/max32/CMakeLists.txt b/soc/adi/max32/CMakeLists.txt
new file mode 100644
index 00000000000..9941c670e8b
--- /dev/null
+++ b/soc/adi/max32/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Copyright (c) 2023-2024 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(${ZEPHYR_BASE}/drivers)
+zephyr_include_directories(common)
+zephyr_sources(soc.c)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/adi/max32/Kconfig b/soc/adi/max32/Kconfig
new file mode 100644
index 00000000000..d968c165af6
--- /dev/null
+++ b/soc/adi/max32/Kconfig
@@ -0,0 +1,29 @@
+# Analog Devices MAX32xxx MCU family
+
+# Copyright (c) 2023-2024 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_MAX32
+	select ARM
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
+	select CPU_CORTEX_M_HAS_SYSTICK
+	select CLOCK_CONTROL
+	select BUILD_OUTPUT_HEX
+
+config SOC_MAX32690
+	select CPU_CORTEX_M4
+
+if SOC_FAMILY_MAX32
+
+config MAX32_ON_ENTER_CPU_IDLE_HOOK
+	bool "CPU idle hook enable"
+	default y
+	imply ARM_ON_ENTER_CPU_IDLE_HOOK
+	help
+	  Enables a hook (z_arm_on_enter_cpu_idle()) that is called when
+	  the CPU is made idle (by k_cpu_idle() or k_cpu_atomic_idle()).
+	  If needed, this hook can be used to prevent the CPU from actually
+	  entering sleep by skipping the WFE/WFI instruction.
+
+endif # SOC_FAMILY_MAX32
diff --git a/soc/adi/max32/Kconfig.defconfig b/soc/adi/max32/Kconfig.defconfig
new file mode 100644
index 00000000000..eb33fc2daa9
--- /dev/null
+++ b/soc/adi/max32/Kconfig.defconfig
@@ -0,0 +1,13 @@
+# Analog Devices MAX32xxx MCU family
+
+# Copyright (c) 2023-2024 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_FAMILY_MAX32
+
+rsource "Kconfig.defconfig.max32*"
+
+config SRAM_VECTOR_TABLE
+	default y
+
+endif # SOC_FAMILY_MAX32
diff --git a/soc/adi/max32/Kconfig.defconfig.max32690 b/soc/adi/max32/Kconfig.defconfig.max32690
new file mode 100644
index 00000000000..a82759aff09
--- /dev/null
+++ b/soc/adi/max32/Kconfig.defconfig.max32690
@@ -0,0 +1,14 @@
+# Analog Devices MAX32690 MCU
+
+# Copyright (c) 2023-2024 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_MAX32690
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/clocks/clk_ipo,clock-frequency)
+
+config NUM_IRQS
+	default 112
+
+endif # SOC_MAX32690
diff --git a/soc/adi/max32/Kconfig.soc b/soc/adi/max32/Kconfig.soc
new file mode 100644
index 00000000000..641af7c7576
--- /dev/null
+++ b/soc/adi/max32/Kconfig.soc
@@ -0,0 +1,21 @@
+# Analog Devices MAX32xxx MCU family
+
+# Copyright (c) 2023-2024 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_MAX32
+	bool
+
+config SOC_FAMILY
+	default "max32" if SOC_FAMILY_MAX32
+
+config SOC_MAX32690
+	bool
+	select SOC_FAMILY_MAX32
+
+config SOC_MAX32690_M4
+	bool
+	select SOC_MAX32690
+
+config SOC
+	default "max32690" if SOC_MAX32690
diff --git a/soc/adi/max32/soc.c b/soc/adi/max32/soc.c
new file mode 100644
index 00000000000..5c7f875d029
--- /dev/null
+++ b/soc/adi/max32/soc.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2023-2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for MAX32xxx MCUs
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+
+#include <wrap_max32_sys.h>
+
+#if defined(CONFIG_MAX32_ON_ENTER_CPU_IDLE_HOOK)
+bool z_arm_on_enter_cpu_idle(void)
+{
+	/* Returning false prevent device goes to sleep mode */
+	return false;
+}
+#endif
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ * So the init priority has to be 0 (zero).
+ *
+ * @return 0
+ */
+static int max32xxx_init(void)
+{
+	/* Apply device related preinit configuration */
+	max32xx_system_init();
+
+	return 0;
+}
+
+SYS_INIT(max32xxx_init, PRE_KERNEL_1, 0);
diff --git a/soc/adi/max32/soc.h b/soc/adi/max32/soc.h
new file mode 100644
index 00000000000..fd785920a4a
--- /dev/null
+++ b/soc/adi/max32/soc.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2023-2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the MAX32xxx family processors.
+ *
+ */
+
+#ifndef _MAX32_SOC_H_
+#define _MAX32_SOC_H_
+
+#include <wrap_max32xxx.h>
+
+#endif /* _MAX32_SOC_H_ */
diff --git a/soc/adi/max32/soc.yml b/soc/adi/max32/soc.yml
new file mode 100644
index 00000000000..a5cba0de349
--- /dev/null
+++ b/soc/adi/max32/soc.yml
@@ -0,0 +1,9 @@
+# Copyright (c) 2023-2024 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+family:
+- name: max32
+  socs:
+  - name: max32690
+    cpuclusters:
+    - name: m4