boards: st: nucleo_u575zi_q: add USB OTG_FS
Add USB OTG_FS on nucleo_u575zi_q Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com> Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
This commit is contained in:
parent
b064a2cfcc
commit
d32a455570
2 changed files with 8 additions and 0 deletions
|
@ -167,6 +167,8 @@ The Zephyr nucleo_u575zi_q board configuration supports the following hardware f
|
|||
+-----------+------------+-------------------------------------+
|
||||
| WATCHDOG | on-chip | independent watchdog |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| USB FS | on-chip | USB Full Speed device |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| BKP SRAM | on-chip | Backup SRAM |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| RNG | on-chip | True Random number generator |
|
||||
|
|
|
@ -171,6 +171,12 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
zephyr_udc0: &usbotg_fs {
|
||||
pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fdcan1 {
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>,
|
||||
<&rcc STM32_SRC_PLL1_Q FDCAN1_SEL(1)>;
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue