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boards: st: nucleo_u575zi_q: add USB OTG_FS

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Add USB OTG_FS on nucleo_u575zi_q

Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
This commit is contained in:
IBEN EL HADJ MESSAOUD Marwa 2024-05-06 13:41:29 +02:00 • committed by Carles Cufí
commit d32a455570
2 changed files with 8 additions and 0 deletions
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2
boards/st/nucleo_u575zi_q/doc/index.rst
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@ -167,6 +167,8 @@ The Zephyr nucleo_u575zi_q board configuration supports the following hardware f
+-----------+------------+-------------------------------------+ +-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | independent watchdog | | WATCHDOG | on-chip | independent watchdog |
+-----------+------------+-------------------------------------+ +-----------+------------+-------------------------------------+
| USB FS | on-chip | USB Full Speed device |
+-----------+------------+-------------------------------------+
| BKP SRAM | on-chip | Backup SRAM | | BKP SRAM | on-chip | Backup SRAM |
+-----------+------------+-------------------------------------+ +-----------+------------+-------------------------------------+
| RNG | on-chip | True Random number generator | | RNG | on-chip | True Random number generator |

6
boards/st/nucleo_u575zi_q/nucleo_u575zi_q-common.dtsi
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@ -171,6 +171,12 @@
status = "okay"; status = "okay";
}; };
zephyr_udc0: &usbotg_fs {
pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
pinctrl-names = "default";
status = "okay";
};
&fdcan1 { &fdcan1 {
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>, clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>,
<&rcc STM32_SRC_PLL1_Q FDCAN1_SEL(1)>; <&rcc STM32_SRC_PLL1_Q FDCAN1_SEL(1)>;