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soc: arm: xilinx_zynqmp: Relocate platform-specific initialisation.

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This commit relocates the exception vector table address range
configuration routine that was previously implemented as part of
Cortex-R architecture reset function to SoC platform-specific
initialisation routine.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit is contained in:
Stephanos Ioannidis 2019-10-16 16:46:48 +09:00 • committed by Ioannis Glaropoulos
commit d314253fbb
2 changed files with 13 additions and 1 deletions
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1
soc/arm/xilinx_zynqmp/Kconfig.soc
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@ -9,3 +9,4 @@ config SOC_XILINX_ZYNQMP_RPU
select GIC_V1 select GIC_V1
select MULTI_LEVEL_INTERRUPTS select MULTI_LEVEL_INTERRUPTS
select 2ND_LEVEL_INTERRUPTS select 2ND_LEVEL_INTERRUPTS
select PLATFORM_SPECIFIC_INIT

13
soc/arm/xilinx_zynqmp/soc.c
View file

@ -9,7 +9,6 @@
#include <device.h> #include <device.h>
#include <init.h> #include <init.h>
#include <arch/cpu.h>
/** /**
* *
* @brief Perform basic hardware initialization * @brief Perform basic hardware initialization
@ -29,3 +28,15 @@ static int soc_init(struct device *arg)
} }
SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
void z_platform_init(void)
{
/*
* Use normal exception vectors address range (0x0-0x1C).
*/
__asm__ volatile(
"mrc p15, 0, r0, c1, c0, 0;" /* SCTLR */
"bic r0, r0, #" TOSTR(HIVECS) ";" /* Clear HIVECS */
"mcr p15, 0, r0, c1, c0, 0;"
: : : "memory");
}