boards: frdm_mcxa153: add frdm_mcxa153 board

add frdm_mcxa153 board support.
Test with samples/hello_world, samples/basic/blinky.

Signed-off-by: Neil Chen <cheng.chen_1@nxp.com>

boards/nxp/frdm_mcxa153/CMakeLists.txt

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+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_library()
+zephyr_library_sources(board.c)

boards/nxp/frdm_mcxa153/Kconfig

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+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_FRDM_MCXA153
+	select BOARD_EARLY_INIT_HOOK

boards/nxp/frdm_mcxa153/Kconfig.frdm_mcxa153

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+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_FRDM_MCXA153
+	select SOC_MCXA153 if BOARD_FRDM_MCXA153
+	select SOC_PART_NUMBER_MCXA153VLH

boards/nxp/frdm_mcxa153/board.c

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+/*
+ * Copyright 2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/init.h>
+#include <zephyr/device.h>
+#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
+#include <fsl_clock.h>
+#include <fsl_spc.h>
+#include <soc.h>
+
+/* Core clock frequency: 96MHz */
+#define CLOCK_INIT_CORE_CLOCK            960000000U
+#define BOARD_BOOTCLOCKFRO96M_CORE_CLOCK 960000000U
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+void board_early_init_hook(void)
+{
+	uint32_t coreFreq;
+	spc_active_mode_core_ldo_option_t ldoOption;
+	spc_sram_voltage_config_t sramOption;
+
+	/* Get the CPU Core frequency */
+	coreFreq = CLOCK_GetCoreSysClkFreq();
+
+	/* The flow of increasing voltage and frequency */
+	if (coreFreq <= BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) {
+		/* Set the LDO_CORE VDD regulator level */
+		ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
+		ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+		(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+		/* Configure Flash to support different voltage level and frequency */
+		FMU0->FCTRL =
+			(FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));
+		/* Specifies the operating voltage for the SRAM's read/write timing margin */
+		sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
+		sramOption.requestVoltageUpdate = true;
+		(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+	}
+
+	CLOCK_SetupFROHFClocking(CLOCK_INIT_CORE_CLOCK); /*!< Enable FRO HF(96MHz) output */
+
+	CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
+
+	CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */
+
+	/* The flow of decreasing voltage and frequency */
+	if (coreFreq > BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) {
+		/* Configure Flash to support different voltage level and frequency */
+		FMU0->FCTRL =
+			(FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));
+		/* Specifies the operating voltage for the SRAM's read/write timing margin */
+		sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
+		sramOption.requestVoltageUpdate = true;
+		(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+		/* Set the LDO_CORE VDD regulator level */
+		ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
+		ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+		(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+	}
+
+	/*!< Set up clock selectors - Attach clocks to the peripheries */
+
+	/*!< Set up dividers */
+	CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U);     /* !< Set AHBCLKDIV divider to value 1 */
+	CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio0))
+	RESET_ReleasePeripheralReset(kGPIO0_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GateGPIO0);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio1))
+	RESET_ReleasePeripheralReset(kGPIO1_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GateGPIO1);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio2))
+	RESET_ReleasePeripheralReset(kGPIO2_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GateGPIO2);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio3))
+	RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GateGPIO3);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart0))
+	CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
+	CLOCK_AttachClk(kFRO12M_to_LPUART0);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart1))
+	CLOCK_SetClockDiv(kCLOCK_DivLPUART1, 1u);
+	CLOCK_AttachClk(kFRO12M_to_LPUART1);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(porta))
+	RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portb))
+	RESET_ReleasePeripheralReset(kPORT1_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portc))
+	RESET_ReleasePeripheralReset(kPORT2_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portd))
+	RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn);
+#endif
+
+	/* Set SystemCoreClock variable. */
+	SystemCoreClock = CLOCK_INIT_CORE_CLOCK;
+}

boards/nxp/frdm_mcxa153/board.cmake

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+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+board_runner_args(jlink "--device=MCXA153")
+board_runner_args(linkserver "--device=MCXA153:FRDM-MCXA153")
+board_runner_args(pyocd "--target=mcxA153")
+
+include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)

boards/nxp/frdm_mcxa153/board.yml

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+board:
+  name: frdm_mcxa153
+  full_name: FRDM-MCXA153
+  vendor: nxp
+  socs:
+  - name: mcxa153

boards/nxp/frdm_mcxa153/doc/index.rst

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+.. zephyr:board:: frdm_mcxa153
+
+Overview
+********
+
+FRDM-MCXA153 are compact and scalable development boards for rapid prototyping of
+MCX A14x and A15x MCUs. They offer industry standard headers for easy access
+to the MCU's I/Os, integrated open-standard serial interfaces, external flash
+memory and an on-board MCU-Link debugger. Additional tools like NXP's Expansion
+Board Hub for add-on boards and the Application Code Hub for software examples
+are available through the MCUXpresso Developer Experience.
+
+Hardware
+********
+
+- MCX-A153 Arm Cortex-M33 microcontroller running at 96 MHz
+- 128KB dual-bank on chip Flash
+- 32 KB RAM
+- USB full-speed with on-chip FS PHY. USB Type-C connectors
+- 1x I3C
+- On-board MCU-Link debugger with CMSIS-DAP
+- Arduino Header, mikroBUS
+
+For more information about the MCX-A153 SoC and FRDM-MCXA153 board, see:
+
+- `MCX-A153 SoC Website`_
+- `MCX-A153 Datasheet`_
+- `MCX-A153 Reference Manual`_
+- `FRDM-MCXA153 Website`_
+- `FRDM-MCXA153 User Guide`_
+- `FRDM-MCXA153 Board User Manual`_
+- `FRDM-MCXA153 Schematics`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
+The MCX-A153 SoC has 4 gpio controllers and has pinmux registers which
+can be used to configure the functionality of a pin.
+
++------------+-----------------+----------------------------+
+| Name       | Function        | Usage                      |
++============+=================+============================+
+| PIO0_2     | UART            | UART RX                    |
++------------+-----------------+----------------------------+
+| PIO0_3     | UART            | UART TX                    |
++------------+-----------------+----------------------------+
+
+System Clock
+============
+
+The MCX-A153 SoC is configured to use FRO running at 96MHz as a source for
+the system clock.
+
+Serial Port
+===========
+
+The FRDM-MCXA153 SoC has 3 LPUART interfaces for serial communication.
+LPUART 0 is configured as UART for the console.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+Configuring a Debug Probe
+=========================
+
+A debug probe is used for both flashing and debugging the board. This board is
+configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe.
+
+Using LinkServer
+----------------
+
+Linkserver is the default runner for this board, and supports the factory
+default MCU-Link firmware. Follow the instructions in
+:ref:`mcu-link-cmsis-onboard-debug-probe` to reprogram the default MCU-Link
+firmware. This only needs to be done if the default onboard debug circuit
+firmware was changed. To put the board in ``ISP mode`` to program the firmware,
+short jumper JP8.
+
+Using J-Link
+------------
+
+There are two options. The onboard debug circuit can be updated with Segger
+J-Link firmware by following the instructions in
+:ref:`mcu-link-jlink-onboard-debug-probe`.
+To be able to program the firmware, you need to put the board in ``ISP mode``
+by shorting the jumper JP8.
+The second option is to attach a :ref:`jlink-external-debug-probe` to the
+10-pin SWD connector (J18) of the board. Additionally, the jumper JP20 must
+be shorted.
+For both options use the ``-r jlink`` option with west to use the jlink runner.
+
+.. code-block:: console
+
+   west flash -r jlink
+
+Configuring a Console
+=====================
+
+Connect a USB cable from your PC to J15, and use the serial terminal of your choice
+(minicom, putty, etc.) with the following settings:
+
+- Speed: 115200
+- Data: 8 bits
+- Parity: None
+- Stop bits: 1
+
+Flashing
+========
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: frdm_mcxa153
+   :goals: flash
+
+Open a serial terminal, reset the board (press the RESET button), and you should
+see the following message in the terminal:
+
+.. code-block:: console
+
+   *** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 ***
+   Hello World! frdm_mcxa3/mcxa153
+
+Debugging
+=========
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: frdm_mcxa153/mcxa153
+   :goals: debug
+
+Open a serial terminal, step through the application in your debugger, and you
+should see the following message in the terminal:
+
+.. code-block:: console
+
+   *** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 ***
+   Hello World! frdm_mcxa153/mcxa153
+
+Troubleshooting
+===============
+
+.. include:: ../../common/segger-ecc-systemview.rst
+   :start-after: segger-ecc-systemview
+
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
+.. _MCX-A153 SoC Website:
+   https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-a-series-microcontrollers/mcx-a13x-14x-15x-mcus-with-arm-cortex-m33-scalable-device-options-low-power-and-intelligent-peripherals:MCX-A13X-A14X-A15X
+
+.. _MCX-A153 Datasheet:
+   https://www.nxp.com/docs/en/data-sheet/MCXAP64M96FS3.pdf
+
+.. _MCX-A153 Reference Manual:
+   https://www.nxp.com/webapp/Download?colCode=MCXAP64M96FS3RM
+
+.. _FRDM-MCXA153 Website:
+   https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-MCXA153
+
+.. _FRDM-MCXA153 User Guide:
+   https://www.nxp.com/document/guide/getting-started-with-frdm-mcxa153:GS-FRDM-MCXAXX
+
+.. _FRDM-MCXA153 Board User Manual:
+   https://www.nxp.com/docs/en/user-manual/UM12012.pdf
+
+.. _FRDM-MCXA153 Schematics:
+   https://www.nxp.com/webapp/Download?colCode=SPF-90829_A1

boards/nxp/frdm_mcxa153/frdm_mcxa153-pinctrl.dtsi

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+/*
+ * Copyright 2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#include <nxp/mcx/MCXA153VLH-pinctrl.h>
+
+&pinctrl {
+	pinmux_lpuart0: pinmux_lpuart0 {
+		group0 {
+			pinmux = <LPUART0_RXD_P0_2>,
+				<LPUART0_TXD_P0_3>;
+			drive-strength = "low";
+			slew-rate = "fast";
+			input-enable;
+		};
+	};
+};

boards/nxp/frdm_mcxa153/frdm_mcxa153.dts

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+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_mcxa153.dtsi>
+#include "frdm_mcxa153-pinctrl.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "NXP FRDM_MCXA153 board";
+	compatible = "nxp,mcxa153", "nxp,mcx";
+
+	aliases{
+		led0 = &red_led;
+		led1 = &green_led;
+		led2 = &blue_led;
+		sw0 = &user_button_2;
+		sw1 = &user_button_3;
+	};
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash;
+		zephyr,flash-controller = &fmu;
+		zephyr,console = &lpuart0;
+		zephyr,shell-uart = &lpuart0;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		red_led: led_0 {
+			gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
+			label = "Red LED";
+		};
+
+		green_led: led_1 {
+			gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
+			label = "Green LED";
+		};
+
+		blue_led: led_2 {
+			gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
+			label = "Blue LED";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		user_button_2: button_2 {
+			label = "User SW2";
+			gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		user_button_3: button_3 {
+			label = "User SW3";
+			gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+			zephyr,code = <INPUT_KEY_1>;
+		};
+	};
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&lpuart0 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&pinmux_lpuart0>;
+	pinctrl-names = "default";
+};

boards/nxp/frdm_mcxa153/frdm_mcxa153.yaml

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+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: frdm_mcxa153
+name: NXP FRDM MCXA153
+type: mcu
+arch: arm
+ram: 24
+flash: 128
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - gpio
+  - uart
+vendor: nxp

boards/nxp/frdm_mcxa153/frdm_mcxa153_defconfig

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+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_GPIO=y