arch/x86: split Kconfig files by sub-architecture
Separate common, ia32 (32-bit) and x64 (64-bit long mode) options. Signed-off-by: Charles E. Youse <charles.youse@intel.com>
This commit is contained in:
Charles E. Youse
Anas Nashif
parent
4fe7f69182
commit
d2b33a486b
4 changed files with 453 additions and 437 deletions
381
arch/x86/Kconfig
381
arch/x86/Kconfig
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@ -11,6 +11,61 @@ menu "X86 Architecture Options"
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config ARCH
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config ARCH
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default "x86"
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default "x86"
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#
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# CPU Families - the SoC configuration should select the right one.
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#
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config CPU_ATOM
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bool # hidden
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select CPU_HAS_FPU
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select ARCH_HAS_STACK_PROTECTION if X86_MMU
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select ARCH_HAS_USERSPACE if X86_MMU
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help
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This option signifies the use of a CPU from the Atom family.
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config CPU_MINUTEIA
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bool # hidden
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select ARCH_HAS_STACK_PROTECTION if X86_MMU
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select ARCH_HAS_USERSPACE if X86_MMU
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help
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This option signifies the use of a CPU from the Minute IA family.
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config CPU_APOLLO_LAKE
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bool # hidden
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select CPU_HAS_FPU
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select ARCH_HAS_STACK_PROTECTION if X86_MMU
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select ARCH_HAS_USERSPACE if X86_MMU
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help
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This option signifies the use of a CPU from the Apollo Lake family.
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#
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# Configuration common to both IA32 and X64 sub-architectures.
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#
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config X86_LONGMODE
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bool
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prompt "Run in long (64-bit) mode"
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default n
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config XIP
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default n
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config PIC_DISABLE
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bool "Disable PIC"
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help
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This option disables all interrupts on the legacy i8259 PICs at boot.
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choice
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prompt "Reboot implementation"
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depends on REBOOT
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default REBOOT_RST_CNT
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config REBOOT_RST_CNT
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bool "Reboot via RST_CNT register"
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help
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Reboot via the RST_CNT register, going back to BIOS.
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endchoice
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config X86_MULTIBOOT
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config X86_MULTIBOOT
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bool "Generate multiboot header"
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bool "Generate multiboot header"
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default y
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default y
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@ -53,329 +108,7 @@ endif # X86_MULTIBOOT_FRAMEBUF
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endif # X86_MULTIBOOT
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endif # X86_MULTIBOOT
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source "arch/x86/core/Kconfig"
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source "arch/x86/core/Kconfig.ia32"
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source "arch/x86/core/Kconfig.x64"
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#
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# Hidden CPU family configs which are to be selected by
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# individual SoC.
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#
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config CPU_ATOM
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# Hidden
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bool
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select CPU_HAS_FPU
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select ARCH_HAS_STACK_PROTECTION if X86_MMU
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select ARCH_HAS_USERSPACE if X86_MMU
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help
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This option signifies the use of a CPU from the Atom family.
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config CPU_MINUTEIA
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# Hidden
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select ARCH_HAS_STACK_PROTECTION if X86_MMU
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select ARCH_HAS_USERSPACE if X86_MMU
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bool
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help
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This option signifies the use of a CPU from the Minute IA family.
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config CPU_APOLLO_LAKE
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# Hidden
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bool
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select CPU_HAS_FPU
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select ARCH_HAS_STACK_PROTECTION if X86_MMU
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select ARCH_HAS_USERSPACE if X86_MMU
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help
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This option signifies the use of a CPU from the Apollo Lake family.
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menu "Processor Capabilities"
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config X86_IAMCU
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bool "IAMCU calling convention"
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help
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The IAMCU calling convention changes the X86 C calling convention to
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pass some arguments via registers allowing for code size and performance
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improvements. Great care needs to be taken if you have assembly code
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that will be called from C or C code called from assembly code, the
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assembly code will need to be updated to conform to the new calling
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convention. If in doubt say N
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config X86_MMU
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bool "Enable Memory Management Unit"
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select MEMORY_PROTECTION
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help
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This options enables the memory management unit present in x86
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and creates a set of page tables at build time. Requires an MMU
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which supports PAE page tables.
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config X86_NO_MELTDOWN
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bool
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help
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This hidden option should be set on a per-SOC basis to indicate that
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a particular SOC is not vulnerable to the Meltdown CPU vulnerability,
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as described in CVE-2017-5754.
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config X86_NO_SPECTRE_V1
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bool
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help
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This hidden option should be set on a per-SOC basis to indicate that
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a particular SOC is not vulnerable to the Spectre V1, V1.1, and V1.2
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CPU vulnerabilities as described in CVE-2017-5753 and CVE-2018-3693.
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config X86_NO_SPECTRE_V2
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bool
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help
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This hidden option should be set on a per-SOC basis to indicate that
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a particular SOC is not vulnerable to the Spectre V2 CPU
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vulnerability, as described in CVE-2017-5715.
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config X86_NO_SPECTRE_V4
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bool
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help
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This hidden option should be set on a per-SOC basis to indicate that
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a particular SOC is not vulnerable to the Spectre V4 CPU
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vulnerability, as described in CVE-2018-3639.
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config X86_NO_LAZY_FP
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bool
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help
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This hidden option should be set on a per-SOC basis to indicate
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that a particular SOC is not vulnerable to the Lazy FP CPU
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vulnerability, as described in CVE-2018-3665.
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config X86_NO_SPECULATIVE_VULNERABILITIES
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bool
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select X86_NO_MELTDOWN
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select X86_NO_SPECTRE_V1
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select X86_NO_SPECTRE_V2
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select X86_NO_SPECTRE_V4
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select X86_NO_LAZY_FP
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help
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This hidden option should be set on a per-SOC basis to indicate that
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a particular SOC does not perform any kind of speculative execution,
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or is a newer chip which is immune to the class of vulnerabilities
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which exploit speculative execution side channel attacks.
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config X86_ENABLE_TSS
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bool
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help
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This hidden option enables defining a Task State Segment (TSS) for
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kernel execution. This is needed to handle double-faults or
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do privilege elevation. It also defines a special TSS and handler
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for correctly handling double-fault exceptions, instead of just
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letting the system triple-fault and reset.
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config X86_STACK_PROTECTION
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bool
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default y if HW_STACK_PROTECTION
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select SET_GDT
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select GDT_DYNAMIC
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select X86_ENABLE_TSS
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help
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This option leverages the MMU to cause a system fatal error if the
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bounds of the current process stack are overflowed. This is done
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by preceding all stack areas with a 4K guard page.
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config X86_USERSPACE
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bool
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default y if USERSPACE
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select THREAD_STACK_INFO
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select SET_GDT
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select GDT_DYNAMIC
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select X86_ENABLE_TSS
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help
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This option enables APIs to drop a thread's privileges down to ring 3,
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supporting user-level threads that are protected from each other and
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from crashing the kernel.
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config X86_KPTI
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bool "Enable kernel page table isolation"
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default y
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depends on USERSPACE
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depends on !X86_NO_MELTDOWN
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help
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Implements kernel page table isolation to mitigate Meltdown exploits
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to read Kernel RAM. Incurs a significant performance cost for
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user thread interrupts and system calls, and significant footprint
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increase for additional page tables and trampoline stacks.
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menu "Architecture Floating Point Options"
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depends on CPU_HAS_FPU
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config SSE
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bool "SSE registers"
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depends on FLOAT
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help
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This option enables the use of SSE registers by threads.
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config SSE_FP_MATH
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bool "Compiler-generated SSEx instructions"
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depends on SSE
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help
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This option allows the compiler to generate SSEx instructions for
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performing floating point math. This can greatly improve performance
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when exactly the same operations are to be performed on multiple
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data objects; however, it can also significantly reduce performance
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when preemptive task switches occur because of the larger register
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set that must be saved and restored.
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Disabling this option means that the compiler utilizes only the
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x87 instruction set for floating point operations.
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config EAGER_FP_SHARING
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bool
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depends on FLOAT
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depends on USERSPACE
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default y if !X86_NO_LAZY_FP
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help
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This hidden option unconditionally saves/restores the FPU/SIMD
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register state on every context switch.
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Mitigates CVE-2018-3665, but incurs a performance hit.
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For vulnerable systems that process sensitive information in the
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FPU register set, should be used any time CONFIG_FLOAT is
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enabled, regardless if the FPU is used by one thread or multiple.
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config LAZY_FP_SHARING
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bool
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depends on FLOAT
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depends on !EAGER_FP_SHARING
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depends on FP_SHARING
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default y if X86_NO_LAZY_FP || !USERSPACE
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help
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This hidden option allows multiple threads to use the floating point
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registers, using logic to lazily save/restore the floating point
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register state on context switch.
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On Intel Core procesors, may be vulnerable to exploits which allows
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malware to read the contents of all floating point registers, see
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CVE-2018-3665.
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endmenu
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choice
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prompt "Reboot implementation"
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depends on REBOOT
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default REBOOT_RST_CNT
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config REBOOT_RST_CNT
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bool "Reboot via RST_CNT register"
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help
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Reboot via the RST_CNT register, going back to BIOS.
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endchoice
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config CACHE_LINE_SIZE_DETECT
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bool "Detect cache line size at runtime"
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default y
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help
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This option enables querying the CPUID register for finding the cache line
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size at the expense of taking more memory and code and a slightly increased
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boot time.
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If the CPU's cache line size is known in advance, disable this option and
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manually enter the value for CACHE_LINE_SIZE.
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config CACHE_LINE_SIZE
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int "Cache line size" if !CACHE_LINE_SIZE_DETECT
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default 64 if CPU_ATOM
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default 0
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help
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Size in bytes of a CPU cache line.
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Detect automatically at runtime by selecting CACHE_LINE_SIZE_DETECT.
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config CLFLUSH_INSTRUCTION_SUPPORTED
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bool "CLFLUSH instruction supported"
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depends on !CLFLUSH_DETECT && CACHE_FLUSHING
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help
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An implementation of sys_cache_flush() that uses CLFLUSH is made
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available, instead of the one using WBINVD.
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This option should only be enabled if it is known in advance that the
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CPU supports the CLFLUSH instruction. It disables runtime detection of
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CLFLUSH support thereby reducing both memory footprint and boot time.
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config CLFLUSH_DETECT
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bool "Detect support of CLFLUSH instruction at runtime"
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depends on CACHE_FLUSHING
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help
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This option should be enabled if it is not known in advance whether the
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CPU supports the CLFLUSH instruction or not.
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The CPU is queried at boot time to determine which of the multiple
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implementations of sys_cache_flush() linked into the image is the
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correct one to use.
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If the CPU's support (or lack thereof) of CLFLUSH is known in advance, then
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disable this option and set CLFLUSH_INSTRUCTION_SUPPORTED as appropriate.
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config ARCH_CACHE_FLUSH_DETECT
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bool
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default y
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depends on CLFLUSH_DETECT
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config CACHE_FLUSHING
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bool "Enable cache flushing mechanism"
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help
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This links in the sys_cache_flush() function. A mechanism for flushing the
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cache must be selected as well. By default, that mechanism is discovered at
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runtime.
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config PIC_DISABLE
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bool "Disable PIC"
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help
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This option disables all interrupts on the PIC
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config X86_KERNEL_OOPS
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bool "Enable handling of kernel oops as an exception"
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default y
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help
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Enable handling of k_oops() API as a CPU exception, which will provide
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extra debugging information such as program counter and register
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values when the oops is triggered. Requires an entry in the IDT.
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config X86_KERNEL_OOPS_VECTOR
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int "IDT vector to use for kernel oops"
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default 62 if MVIC
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default 33 if !MVIC
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range 32 255
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depends on X86_KERNEL_OOPS
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help
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Specify the IDT vector to use for the kernel oops exception handler.
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The default should be fine for most arches, but on systems like MVIC
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where there is a fixed IRQ-to-vector mapping another value may be
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needed to avoid collision.
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config IRQ_OFFLOAD_VECTOR
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int "IDT vector to use for IRQ offload"
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default 63 if MVIC
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default 32 if !MVIC
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range 32 255
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depends on IRQ_OFFLOAD
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help
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Specify the IDT vector to use for the IRQ offload interrupt handler.
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The default should be fine for most arches, but on systems like MVIC
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where there is a fixed IRQ-to-vector mapping another value may be
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needed to avoid collision.
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config X86_DYNAMIC_IRQ_STUBS
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int "Number of dynamic interrupt stubs"
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depends on DYNAMIC_INTERRUPTS
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default 4
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help
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Installing interrupt handlers with irq_connect_dynamic() requires
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some stub code to be generated at build time, one stub per dynamic
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interrupt.
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config XIP
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default n
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config X86_FIXED_IRQ_MAPPING
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bool
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help
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Specify whether the current interrupt controller in use has a fixed
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mapping between IDT vectors and IRQ lines.
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endmenu
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endmenu
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endmenu
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@ -1,113 +0,0 @@
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# Kconfig - x86 core configuration options
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#
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# Copyright (c) 2014-2015 Wind River Systems, Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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|
||||||
#
|
|
||||||
|
|
||||||
config NESTED_INTERRUPTS
|
|
||||||
bool "Enable nested interrupts"
|
|
||||||
default y
|
|
||||||
help
|
|
||||||
This option enables support for nested interrupts.
|
|
||||||
|
|
||||||
config EXCEPTION_DEBUG
|
|
||||||
bool "Unhandled exception debugging"
|
|
||||||
default y
|
|
||||||
depends on PRINTK
|
|
||||||
help
|
|
||||||
Install handlers for various CPU exception/trap vectors to
|
|
||||||
make debugging them easier, at a small expense in code size.
|
|
||||||
This prints out the specific exception vector and any associated
|
|
||||||
error codes.
|
|
||||||
|
|
||||||
menu "Memory Layout Options"
|
|
||||||
|
|
||||||
config IDT_NUM_VECTORS
|
|
||||||
int "Number of IDT vectors"
|
|
||||||
default 256
|
|
||||||
range 32 256
|
|
||||||
help
|
|
||||||
This option specifies the number of interrupt vector entries in the
|
|
||||||
Interrupt Descriptor Table (IDT). By default all 256 vectors are
|
|
||||||
supported in an IDT requiring 2048 bytes of memory.
|
|
||||||
|
|
||||||
config MAX_IRQ_LINES
|
|
||||||
int "Number of IRQ lines"
|
|
||||||
default 128
|
|
||||||
range 0 256
|
|
||||||
help
|
|
||||||
This option specifies the number of IRQ lines in the system.
|
|
||||||
It can be tuned to save some bytes in ROM, as it determines the
|
|
||||||
size of the _irq_to_interrupt_vector_table, which is used at runtime
|
|
||||||
to program to the PIC the association between vectors and
|
|
||||||
interrupts.
|
|
||||||
|
|
||||||
config SET_GDT
|
|
||||||
bool "Setup GDT as part of boot process"
|
|
||||||
default y
|
|
||||||
help
|
|
||||||
This option sets up the GDT as part of the boot process. However,
|
|
||||||
this may conflict with some security scenarios where the GDT is
|
|
||||||
already appropriately set by an earlier bootloader stage, in which
|
|
||||||
case this should be disabled. If disabled, the global _gdt pointer
|
|
||||||
will not be available.
|
|
||||||
|
|
||||||
config GDT_DYNAMIC
|
|
||||||
bool "Store GDT in RAM so that it can be modified"
|
|
||||||
depends on SET_GDT
|
|
||||||
help
|
|
||||||
This option stores the GDT in RAM instead of ROM, so that it may
|
|
||||||
be modified at runtime at the expense of some memory.
|
|
||||||
|
|
||||||
endmenu
|
|
||||||
|
|
||||||
config DISABLE_SSBD
|
|
||||||
bool "Disable Speculative Store Bypass"
|
|
||||||
depends on USERSPACE
|
|
||||||
default y if !X86_NO_SPECTRE_V4
|
|
||||||
help
|
|
||||||
This option will disable Speculative Store Bypass in order to
|
|
||||||
mitigate against certain kinds of side channel attacks. Quoting
|
|
||||||
the "Speculative Execution Side Channels" document, version 2.0:
|
|
||||||
|
|
||||||
When SSBD is set, loads will not execute speculatively
|
|
||||||
until the addresses of all older stores are known. This
|
|
||||||
ensure s that a load does not speculatively consume stale
|
|
||||||
data values due to bypassing an older store on the same
|
|
||||||
logical processor.
|
|
||||||
|
|
||||||
If enabled, this applies to all threads in the system.
|
|
||||||
|
|
||||||
Even if enabled, will have no effect on CPUs that do not
|
|
||||||
require this feature.
|
|
||||||
|
|
||||||
config ENABLE_EXTENDED_IBRS
|
|
||||||
bool "Enable Extended IBRS"
|
|
||||||
depends on USERSPACE
|
|
||||||
default y if !X86_NO_SPECTRE_V2
|
|
||||||
help
|
|
||||||
This option will enable the Extended Indirect Branch Restricted
|
|
||||||
Speculation 'always on' feature. This mitigates Indirect Branch
|
|
||||||
Control vulnerabilities (aka Spectre V2).
|
|
||||||
|
|
||||||
config X86_RETPOLINE
|
|
||||||
bool "Build with retpolines enabled in x86 assembly code"
|
|
||||||
depends on USERSPACE
|
|
||||||
help
|
|
||||||
This is recommended on platforms with speculative executions, to
|
|
||||||
protect against branch target injection (AKA Spectre-V2). Full
|
|
||||||
description of how retpolines work can be found here[1].
|
|
||||||
|
|
||||||
[1] https://support.google.com/faqs/answer/7625886
|
|
||||||
|
|
||||||
config X86_BOUNDS_CHECK_BYPASS_MITIGATION
|
|
||||||
bool
|
|
||||||
depends on USERSPACE
|
|
||||||
default y if !X86_NO_SPECTRE_V1
|
|
||||||
select BOUNDS_CHECK_BYPASS_MITIGATION
|
|
||||||
help
|
|
||||||
Hidden config to select arch-independent option to enable
|
|
||||||
Spectre V1 mitigations by default if the CPU is not known
|
|
||||||
to be immune to it.
|
|
||||||
387
arch/x86/core/Kconfig.ia32
Normal file
387
arch/x86/core/Kconfig.ia32
Normal file
|
|
@ -0,0 +1,387 @@
|
||||||
|
# Kconfig.ia32 - IA32-specific X86 subarchitecture options
|
||||||
|
#
|
||||||
|
# Copyright (c) 2019 Intel Corp.
|
||||||
|
# SPDX-License-Identifier: Apache-2.0
|
||||||
|
#
|
||||||
|
|
||||||
|
if !X86_LONGMODE
|
||||||
|
|
||||||
|
config NESTED_INTERRUPTS
|
||||||
|
bool "Enable nested interrupts"
|
||||||
|
default y
|
||||||
|
help
|
||||||
|
This option enables support for nested interrupts.
|
||||||
|
|
||||||
|
config EXCEPTION_DEBUG
|
||||||
|
bool "Unhandled exception debugging"
|
||||||
|
default y
|
||||||
|
depends on PRINTK
|
||||||
|
help
|
||||||
|
Install handlers for various CPU exception/trap vectors to
|
||||||
|
make debugging them easier, at a small expense in code size.
|
||||||
|
This prints out the specific exception vector and any associated
|
||||||
|
error codes.
|
||||||
|
|
||||||
|
menu "Memory Layout Options"
|
||||||
|
|
||||||
|
config IDT_NUM_VECTORS
|
||||||
|
int "Number of IDT vectors"
|
||||||
|
default 256
|
||||||
|
range 32 256
|
||||||
|
help
|
||||||
|
This option specifies the number of interrupt vector entries in the
|
||||||
|
Interrupt Descriptor Table (IDT). By default all 256 vectors are
|
||||||
|
supported in an IDT requiring 2048 bytes of memory.
|
||||||
|
|
||||||
|
config MAX_IRQ_LINES
|
||||||
|
int "Number of IRQ lines"
|
||||||
|
default 128
|
||||||
|
range 0 256
|
||||||
|
help
|
||||||
|
This option specifies the number of IRQ lines in the system.
|
||||||
|
It can be tuned to save some bytes in ROM, as it determines the
|
||||||
|
size of the _irq_to_interrupt_vector_table, which is used at runtime
|
||||||
|
to program to the PIC the association between vectors and
|
||||||
|
interrupts.
|
||||||
|
|
||||||
|
config SET_GDT
|
||||||
|
bool "Setup GDT as part of boot process"
|
||||||
|
default y
|
||||||
|
help
|
||||||
|
This option sets up the GDT as part of the boot process. However,
|
||||||
|
this may conflict with some security scenarios where the GDT is
|
||||||
|
already appropriately set by an earlier bootloader stage, in which
|
||||||
|
case this should be disabled. If disabled, the global _gdt pointer
|
||||||
|
will not be available.
|
||||||
|
|
||||||
|
config GDT_DYNAMIC
|
||||||
|
bool "Store GDT in RAM so that it can be modified"
|
||||||
|
depends on SET_GDT
|
||||||
|
help
|
||||||
|
This option stores the GDT in RAM instead of ROM, so that it may
|
||||||
|
be modified at runtime at the expense of some memory.
|
||||||
|
|
||||||
|
endmenu
|
||||||
|
|
||||||
|
config DISABLE_SSBD
|
||||||
|
bool "Disable Speculative Store Bypass"
|
||||||
|
depends on USERSPACE
|
||||||
|
default y if !X86_NO_SPECTRE_V4
|
||||||
|
help
|
||||||
|
This option will disable Speculative Store Bypass in order to
|
||||||
|
mitigate against certain kinds of side channel attacks. Quoting
|
||||||
|
the "Speculative Execution Side Channels" document, version 2.0:
|
||||||
|
|
||||||
|
When SSBD is set, loads will not execute speculatively
|
||||||
|
until the addresses of all older stores are known. This
|
||||||
|
ensure s that a load does not speculatively consume stale
|
||||||
|
data values due to bypassing an older store on the same
|
||||||
|
logical processor.
|
||||||
|
|
||||||
|
If enabled, this applies to all threads in the system.
|
||||||
|
|
||||||
|
Even if enabled, will have no effect on CPUs that do not
|
||||||
|
require this feature.
|
||||||
|
|
||||||
|
config ENABLE_EXTENDED_IBRS
|
||||||
|
bool "Enable Extended IBRS"
|
||||||
|
depends on USERSPACE
|
||||||
|
default y if !X86_NO_SPECTRE_V2
|
||||||
|
help
|
||||||
|
This option will enable the Extended Indirect Branch Restricted
|
||||||
|
Speculation 'always on' feature. This mitigates Indirect Branch
|
||||||
|
Control vulnerabilities (aka Spectre V2).
|
||||||
|
|
||||||
|
config X86_RETPOLINE
|
||||||
|
bool "Build with retpolines enabled in x86 assembly code"
|
||||||
|
depends on USERSPACE
|
||||||
|
help
|
||||||
|
This is recommended on platforms with speculative executions, to
|
||||||
|
protect against branch target injection (AKA Spectre-V2). Full
|
||||||
|
description of how retpolines work can be found here[1].
|
||||||
|
|
||||||
|
[1] https://support.google.com/faqs/answer/7625886
|
||||||
|
|
||||||
|
config X86_BOUNDS_CHECK_BYPASS_MITIGATION
|
||||||
|
bool
|
||||||
|
depends on USERSPACE
|
||||||
|
default y if !X86_NO_SPECTRE_V1
|
||||||
|
select BOUNDS_CHECK_BYPASS_MITIGATION
|
||||||
|
help
|
||||||
|
Hidden config to select arch-independent option to enable
|
||||||
|
Spectre V1 mitigations by default if the CPU is not known
|
||||||
|
to be immune to it.
|
||||||
|
|
||||||
|
menu "Processor Capabilities"
|
||||||
|
|
||||||
|
config X86_IAMCU
|
||||||
|
bool "IAMCU calling convention"
|
||||||
|
help
|
||||||
|
The IAMCU calling convention changes the X86 C calling convention to
|
||||||
|
pass some arguments via registers allowing for code size and performance
|
||||||
|
improvements. Great care needs to be taken if you have assembly code
|
||||||
|
that will be called from C or C code called from assembly code, the
|
||||||
|
assembly code will need to be updated to conform to the new calling
|
||||||
|
convention. If in doubt say N
|
||||||
|
|
||||||
|
config X86_MMU
|
||||||
|
bool "Enable Memory Management Unit"
|
||||||
|
select MEMORY_PROTECTION
|
||||||
|
help
|
||||||
|
This options enables the memory management unit present in x86
|
||||||
|
and creates a set of page tables at build time. Requires an MMU
|
||||||
|
which supports PAE page tables.
|
||||||
|
|
||||||
|
config X86_NO_MELTDOWN
|
||||||
|
bool
|
||||||
|
help
|
||||||
|
This hidden option should be set on a per-SOC basis to indicate that
|
||||||
|
a particular SOC is not vulnerable to the Meltdown CPU vulnerability,
|
||||||
|
as described in CVE-2017-5754.
|
||||||
|
|
||||||
|
config X86_NO_SPECTRE_V1
|
||||||
|
bool
|
||||||
|
help
|
||||||
|
This hidden option should be set on a per-SOC basis to indicate that
|
||||||
|
a particular SOC is not vulnerable to the Spectre V1, V1.1, and V1.2
|
||||||
|
CPU vulnerabilities as described in CVE-2017-5753 and CVE-2018-3693.
|
||||||
|
|
||||||
|
config X86_NO_SPECTRE_V2
|
||||||
|
bool
|
||||||
|
help
|
||||||
|
This hidden option should be set on a per-SOC basis to indicate that
|
||||||
|
a particular SOC is not vulnerable to the Spectre V2 CPU
|
||||||
|
vulnerability, as described in CVE-2017-5715.
|
||||||
|
|
||||||
|
config X86_NO_SPECTRE_V4
|
||||||
|
bool
|
||||||
|
help
|
||||||
|
This hidden option should be set on a per-SOC basis to indicate that
|
||||||
|
a particular SOC is not vulnerable to the Spectre V4 CPU
|
||||||
|
vulnerability, as described in CVE-2018-3639.
|
||||||
|
|
||||||
|
config X86_NO_LAZY_FP
|
||||||
|
bool
|
||||||
|
help
|
||||||
|
This hidden option should be set on a per-SOC basis to indicate
|
||||||
|
that a particular SOC is not vulnerable to the Lazy FP CPU
|
||||||
|
vulnerability, as described in CVE-2018-3665.
|
||||||
|
|
||||||
|
config X86_NO_SPECULATIVE_VULNERABILITIES
|
||||||
|
bool
|
||||||
|
select X86_NO_MELTDOWN
|
||||||
|
select X86_NO_SPECTRE_V1
|
||||||
|
select X86_NO_SPECTRE_V2
|
||||||
|
select X86_NO_SPECTRE_V4
|
||||||
|
select X86_NO_LAZY_FP
|
||||||
|
help
|
||||||
|
This hidden option should be set on a per-SOC basis to indicate that
|
||||||
|
a particular SOC does not perform any kind of speculative execution,
|
||||||
|
or is a newer chip which is immune to the class of vulnerabilities
|
||||||
|
which exploit speculative execution side channel attacks.
|
||||||
|
|
||||||
|
config X86_ENABLE_TSS
|
||||||
|
bool
|
||||||
|
help
|
||||||
|
This hidden option enables defining a Task State Segment (TSS) for
|
||||||
|
kernel execution. This is needed to handle double-faults or
|
||||||
|
do privilege elevation. It also defines a special TSS and handler
|
||||||
|
for correctly handling double-fault exceptions, instead of just
|
||||||
|
letting the system triple-fault and reset.
|
||||||
|
|
||||||
|
config X86_STACK_PROTECTION
|
||||||
|
bool
|
||||||
|
default y if HW_STACK_PROTECTION
|
||||||
|
select SET_GDT
|
||||||
|
select GDT_DYNAMIC
|
||||||
|
select X86_ENABLE_TSS
|
||||||
|
help
|
||||||
|
This option leverages the MMU to cause a system fatal error if the
|
||||||
|
bounds of the current process stack are overflowed. This is done
|
||||||
|
by preceding all stack areas with a 4K guard page.
|
||||||
|
|
||||||
|
config X86_USERSPACE
|
||||||
|
bool
|
||||||
|
default y if USERSPACE
|
||||||
|
select THREAD_STACK_INFO
|
||||||
|
select SET_GDT
|
||||||
|
select GDT_DYNAMIC
|
||||||
|
select X86_ENABLE_TSS
|
||||||
|
help
|
||||||
|
This option enables APIs to drop a thread's privileges down to ring 3,
|
||||||
|
supporting user-level threads that are protected from each other and
|
||||||
|
from crashing the kernel.
|
||||||
|
|
||||||
|
config X86_KPTI
|
||||||
|
bool "Enable kernel page table isolation"
|
||||||
|
default y
|
||||||
|
depends on USERSPACE
|
||||||
|
depends on !X86_NO_MELTDOWN
|
||||||
|
help
|
||||||
|
Implements kernel page table isolation to mitigate Meltdown exploits
|
||||||
|
to read Kernel RAM. Incurs a significant performance cost for
|
||||||
|
user thread interrupts and system calls, and significant footprint
|
||||||
|
increase for additional page tables and trampoline stacks.
|
||||||
|
|
||||||
|
menu "Architecture Floating Point Options"
|
||||||
|
depends on CPU_HAS_FPU
|
||||||
|
|
||||||
|
config SSE
|
||||||
|
bool "SSE registers"
|
||||||
|
depends on FLOAT
|
||||||
|
help
|
||||||
|
This option enables the use of SSE registers by threads.
|
||||||
|
|
||||||
|
config SSE_FP_MATH
|
||||||
|
bool "Compiler-generated SSEx instructions"
|
||||||
|
depends on SSE
|
||||||
|
help
|
||||||
|
This option allows the compiler to generate SSEx instructions for
|
||||||
|
performing floating point math. This can greatly improve performance
|
||||||
|
when exactly the same operations are to be performed on multiple
|
||||||
|
data objects; however, it can also significantly reduce performance
|
||||||
|
when preemptive task switches occur because of the larger register
|
||||||
|
set that must be saved and restored.
|
||||||
|
|
||||||
|
Disabling this option means that the compiler utilizes only the
|
||||||
|
x87 instruction set for floating point operations.
|
||||||
|
|
||||||
|
config EAGER_FP_SHARING
|
||||||
|
bool
|
||||||
|
depends on FLOAT
|
||||||
|
depends on USERSPACE
|
||||||
|
default y if !X86_NO_LAZY_FP
|
||||||
|
help
|
||||||
|
This hidden option unconditionally saves/restores the FPU/SIMD
|
||||||
|
register state on every context switch.
|
||||||
|
|
||||||
|
Mitigates CVE-2018-3665, but incurs a performance hit.
|
||||||
|
|
||||||
|
For vulnerable systems that process sensitive information in the
|
||||||
|
FPU register set, should be used any time CONFIG_FLOAT is
|
||||||
|
enabled, regardless if the FPU is used by one thread or multiple.
|
||||||
|
|
||||||
|
config LAZY_FP_SHARING
|
||||||
|
bool
|
||||||
|
depends on FLOAT
|
||||||
|
depends on !EAGER_FP_SHARING
|
||||||
|
depends on FP_SHARING
|
||||||
|
default y if X86_NO_LAZY_FP || !USERSPACE
|
||||||
|
help
|
||||||
|
This hidden option allows multiple threads to use the floating point
|
||||||
|
registers, using logic to lazily save/restore the floating point
|
||||||
|
register state on context switch.
|
||||||
|
|
||||||
|
On Intel Core procesors, may be vulnerable to exploits which allows
|
||||||
|
malware to read the contents of all floating point registers, see
|
||||||
|
CVE-2018-3665.
|
||||||
|
|
||||||
|
endmenu
|
||||||
|
|
||||||
|
config CACHE_LINE_SIZE_DETECT
|
||||||
|
bool "Detect cache line size at runtime"
|
||||||
|
default y
|
||||||
|
help
|
||||||
|
This option enables querying the CPUID register for finding the cache line
|
||||||
|
size at the expense of taking more memory and code and a slightly increased
|
||||||
|
boot time.
|
||||||
|
|
||||||
|
If the CPU's cache line size is known in advance, disable this option and
|
||||||
|
manually enter the value for CACHE_LINE_SIZE.
|
||||||
|
|
||||||
|
config CACHE_LINE_SIZE
|
||||||
|
int "Cache line size" if !CACHE_LINE_SIZE_DETECT
|
||||||
|
default 64 if CPU_ATOM
|
||||||
|
default 0
|
||||||
|
help
|
||||||
|
Size in bytes of a CPU cache line.
|
||||||
|
|
||||||
|
Detect automatically at runtime by selecting CACHE_LINE_SIZE_DETECT.
|
||||||
|
|
||||||
|
config CLFLUSH_INSTRUCTION_SUPPORTED
|
||||||
|
bool "CLFLUSH instruction supported"
|
||||||
|
depends on !CLFLUSH_DETECT && CACHE_FLUSHING
|
||||||
|
help
|
||||||
|
An implementation of sys_cache_flush() that uses CLFLUSH is made
|
||||||
|
available, instead of the one using WBINVD.
|
||||||
|
|
||||||
|
This option should only be enabled if it is known in advance that the
|
||||||
|
CPU supports the CLFLUSH instruction. It disables runtime detection of
|
||||||
|
CLFLUSH support thereby reducing both memory footprint and boot time.
|
||||||
|
|
||||||
|
config CLFLUSH_DETECT
|
||||||
|
bool "Detect support of CLFLUSH instruction at runtime"
|
||||||
|
depends on CACHE_FLUSHING
|
||||||
|
help
|
||||||
|
This option should be enabled if it is not known in advance whether the
|
||||||
|
CPU supports the CLFLUSH instruction or not.
|
||||||
|
|
||||||
|
The CPU is queried at boot time to determine which of the multiple
|
||||||
|
implementations of sys_cache_flush() linked into the image is the
|
||||||
|
correct one to use.
|
||||||
|
|
||||||
|
If the CPU's support (or lack thereof) of CLFLUSH is known in advance, then
|
||||||
|
disable this option and set CLFLUSH_INSTRUCTION_SUPPORTED as appropriate.
|
||||||
|
|
||||||
|
config ARCH_CACHE_FLUSH_DETECT
|
||||||
|
bool
|
||||||
|
default y
|
||||||
|
depends on CLFLUSH_DETECT
|
||||||
|
|
||||||
|
config CACHE_FLUSHING
|
||||||
|
bool "Enable cache flushing mechanism"
|
||||||
|
help
|
||||||
|
This links in the sys_cache_flush() function. A mechanism for flushing the
|
||||||
|
cache must be selected as well. By default, that mechanism is discovered at
|
||||||
|
runtime.
|
||||||
|
|
||||||
|
config X86_KERNEL_OOPS
|
||||||
|
bool "Enable handling of kernel oops as an exception"
|
||||||
|
default y
|
||||||
|
help
|
||||||
|
Enable handling of k_oops() API as a CPU exception, which will provide
|
||||||
|
extra debugging information such as program counter and register
|
||||||
|
values when the oops is triggered. Requires an entry in the IDT.
|
||||||
|
|
||||||
|
config X86_KERNEL_OOPS_VECTOR
|
||||||
|
int "IDT vector to use for kernel oops"
|
||||||
|
default 62 if MVIC
|
||||||
|
default 33 if !MVIC
|
||||||
|
range 32 255
|
||||||
|
depends on X86_KERNEL_OOPS
|
||||||
|
help
|
||||||
|
Specify the IDT vector to use for the kernel oops exception handler.
|
||||||
|
The default should be fine for most arches, but on systems like MVIC
|
||||||
|
where there is a fixed IRQ-to-vector mapping another value may be
|
||||||
|
needed to avoid collision.
|
||||||
|
|
||||||
|
config IRQ_OFFLOAD_VECTOR
|
||||||
|
int "IDT vector to use for IRQ offload"
|
||||||
|
default 63 if MVIC
|
||||||
|
default 32 if !MVIC
|
||||||
|
range 32 255
|
||||||
|
depends on IRQ_OFFLOAD
|
||||||
|
help
|
||||||
|
Specify the IDT vector to use for the IRQ offload interrupt handler.
|
||||||
|
The default should be fine for most arches, but on systems like MVIC
|
||||||
|
where there is a fixed IRQ-to-vector mapping another value may be
|
||||||
|
needed to avoid collision.
|
||||||
|
|
||||||
|
config X86_DYNAMIC_IRQ_STUBS
|
||||||
|
int "Number of dynamic interrupt stubs"
|
||||||
|
depends on DYNAMIC_INTERRUPTS
|
||||||
|
default 4
|
||||||
|
help
|
||||||
|
Installing interrupt handlers with irq_connect_dynamic() requires
|
||||||
|
some stub code to be generated at build time, one stub per dynamic
|
||||||
|
interrupt.
|
||||||
|
|
||||||
|
config X86_FIXED_IRQ_MAPPING
|
||||||
|
bool
|
||||||
|
help
|
||||||
|
Specify whether the current interrupt controller in use has a fixed
|
||||||
|
mapping between IDT vectors and IRQ lines.
|
||||||
|
|
||||||
|
endmenu
|
||||||
|
|
||||||
|
endif # !X86_LONGMODE
|
||||||
9
arch/x86/core/Kconfig.x64
Normal file
9
arch/x86/core/Kconfig.x64
Normal file
|
|
@ -0,0 +1,9 @@
|
||||||
|
# Kconfig.x64 - X64-specific X86 subarchitecture options
|
||||||
|
#
|
||||||
|
# Copyright (c) 2019 Intel Corp.
|
||||||
|
# SPDX-License-Identifier: Apache-2.0
|
||||||
|
#
|
||||||
|
|
||||||
|
if X86_LONGMODE
|
||||||
|
|
||||||
|
endif # X86_LONGMODE
|
||||||
Loading…
Add table
Add a link
Reference in a new issue