boards: nxp_rw612: Add support for u-blox EVK-IRIS-W1x
Add basic board definition of the u-blox EVK-IRIS-W1-rw612 board. Adds maintainer info for u-blox boards. Signed-off-by: Tarang Patel <tarang3399.patel@gmail.com>
This commit is contained in:
parent
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18 changed files with 811 additions and 0 deletions
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@ -4669,6 +4669,15 @@ Tracing:
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tests:
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tests:
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- tracing
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- tracing
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u-blox Platforms:
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status: maintained
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maintainers:
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- 3rang
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files:
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- boards/u-blox/
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labels:
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- "platform: u-blox"
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USB:
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USB:
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status: maintained
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status: maintained
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maintainers:
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maintainers:
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24
boards/u-blox/ubx_evk_iris_w1/CMakeLists.txt
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24
boards/u-blox/ubx_evk_iris_w1/CMakeLists.txt
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#
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#Copyright 2022-2025 NXP
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#Copyright(c)2025 u-blox AG
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#SPDX-License-Identifier:Apache-2.0
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#
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if(CONFIG_NXP_RW6XX_BOOT_HEADER)
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zephyr_compile_definitions(BOARD_FLASH_SIZE=${CONFIG_FLASH_SIZE}*1024)
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if(BOARD_REVISION STREQUAL "macronix")
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zephyr_library_sources(macronix_flash_config.c)
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elseif(BOARD_REVISION STREQUAL "fidelex")
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zephyr_library_sources(fidelex_flash_config.c)
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else()
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message(FATAL_ERROR "Unsupported board revision: ${BOARD_REVISION}")
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endif()
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if(CONFIG_DT_HAS_NXP_ENET_MAC_ENABLED AND CONFIG_XTAL32K)
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message(FATAL_ERROR
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"Ethernet and external 32K clock source are "
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"mutually exclusive on FRDM_RW612 due to shared PCB nets "
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"between the ethernet PHY and the external oscillator")
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endif()
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endif()
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15
boards/u-blox/ubx_evk_iris_w1/Kconfig.defconfig
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15
boards/u-blox/ubx_evk_iris_w1/Kconfig.defconfig
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# SPDX-License-Identifier: Apache-2.0
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# Copyright 2022-2025 NXP
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# Copyright (c) 2025 u-blox AG
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#
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if BOARD_UBX_EVK_IRIS_W1
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if COUNTER_MCUX_LPC_RTC_1HZ
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config XTAL32K
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default y
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endif # COUNTER_MCUX_LPC_RTC_1HZ
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endif # BOARD_UBX_EVK_IRIS_W1
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6
boards/u-blox/ubx_evk_iris_w1/Kconfig.ubx_evk_iris_w1
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6
boards/u-blox/ubx_evk_iris_w1/Kconfig.ubx_evk_iris_w1
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# EVK-IRIS-W1 board configuration
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# Copyright (c) 2025 u-blox AG
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_UBX_EVK_IRIS_W1
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select SOC_PART_NUMBER_RW612ETA2I
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9
boards/u-blox/ubx_evk_iris_w1/board.cmake
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9
boards/u-blox/ubx_evk_iris_w1/board.cmake
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# Copyright 2022-2023 NXP
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# SPDX-License-Identifier: Apache-2.0
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board_runner_args(jlink "--device=RW612" "--reset-after-load")
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board_runner_args(linkserver "--device=RW612:RDRW612")
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
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12
boards/u-blox/ubx_evk_iris_w1/board.yml
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12
boards/u-blox/ubx_evk_iris_w1/board.yml
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board:
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name: ubx_evk_iris_w1
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full_name: EVK-IRIS-W106-RW612
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vendor: u-blox
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revision:
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format: custom
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default: fidelex
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revisions:
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- name: "macronix"
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- name: "fidelex"
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socs:
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- name: rw612
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132
boards/u-blox/ubx_evk_iris_w1/doc/index.rst
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132
boards/u-blox/ubx_evk_iris_w1/doc/index.rst
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.. zephyr:board:: ubx_evk_iris_w1
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Overview
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********
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The EVK-IRIS-W10x evaluation kit enables stand-alone use of the IRIS-W10 series module. This guide
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provides details about the hardware functionality of the EVK-IRIS-W10 board and includes setup
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instructions for starting development.
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All pins and interfaces supported on IRIS-W10 series modules are easily accessible from the
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evaluation board. Simple USB connections serve as the physical interfaces for power, programming
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COM ports, debugging, and USB peripheral connectors. Additionally, the board features other
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interfaces like Ethernet RJ45 and an SDIO header. The EVK-IRIS-W10 board is equipped with a Reset
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button, Boot button, and two user-configurable buttons. Current sense resistors are incorporated for
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accurate current measurement within the module.
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For flexible use, GPIO signals are accessible through headers and are complemented by four
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mikroBUS™ standard slots for convenient utilization of Click boards™. Each Click board can be
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seamlessly plugged into an available mikroBUS™ slot to facilitate effortless hardware expansion with
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a variety of standardized compact add-on boards. Click boards are designed to accommodate a
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diverse range of electronic modules, including sensors, transceivers, displays, encoders, motor
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drivers, connection ports, and more. For further information about the Click boards, visit the MIKROE
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website.
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Hardware
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********
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- 260 MHz ARM Cortex-M33, tri-radio cores for Wi-Fi 6 + BLE 5.3 + 802.15.4
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- 1.2 MB on-chip SRAM
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- EVK-IRIS-W101 evaluation board with IRIS-W101 module. Dual-band PCB antenna for WLAN
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with 100 mm coaxial cable and U.FL connector
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- EVK-IRIS-W106 evaluation board with IRIS-W106 module. Dual-band integrated PCB trace
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antenna (external antenna not supplied)
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Flash Memory Configuration
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==========================
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The IRIS-W1 board uses different flash vendors depending on revision:
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- ``@macronix``: Module build up to 2023 week 45
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- ``@fidelex``: Module build 2023 week 46 (2346) onward
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To build for a specific flash version:
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.. code-block:: bash
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west build -b ubx_evk_iris_w1@macronix
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west build -b ubx_evk_iris_w1@fidelex
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Supported Features
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==================
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.. zephyr:board-supported-hw::
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Basic functionality like UART (default on FC3), GPIOs (I²C, SPI), and the on-board RGB LEDs is supported.
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Programming and Debugging
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*************************
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.. zephyr:board-supported-runners::
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Configuring a Debug Probe
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=========================
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A debug probe is used for both flashing and debugging the board. This board is
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configured by default to use the J-Link firmware.
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Configuring a Console
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=====================
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Connect a USB cable from your PC to USB3, and use the serial terminal of your choice
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(minicom, PuTTY, etc.) with the following settings:
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- Speed: 115200
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- Data: 8 bits
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- Parity: None
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- Stop bits: 1
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Flashing
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========
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Here is an example for the ``hello_world`` application.
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Open a serial terminal, reset the board (press the RESET button), and you should
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see the following message in the terminal:
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.. code-block:: console
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**** Booting Zephyr OS build v4.1.0-2794-g6463c68bc394 ****
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Hello World ! ubx_evk_iris_w1/rw612
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Wireless Connectivity Support
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*****************************
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Fetch Binary Blobs
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==================
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To support Bluetooth or Wi-Fi, ``ubx_evk_iris_w1`` requires fetching binary blobs. This can be
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achieved by running the following command:
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.. code-block:: console
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west blobs fetch hal_nxp
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Bluetooth
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=========
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BLE functionality requires fetching binary blobs, so make sure to follow
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the "Fetch Binary Blobs" section first.
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The required binary blob
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``<zephyr workspace>/modules/hal/nxp/zephyr/blobs/rw61x_sb_ble_a2.bin`` will be linked
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with the application image directly, forming a single monolithic image.
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Wi-Fi
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=====
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Wi-Fi functionality also requires fetching binary blobs, so make sure to follow
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the "Fetch Binary Blobs" section first.
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The required binary blob
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``<zephyr workspace>/modules/hal/nxp/zephyr/blobs/rw61x_sb_wifi_a2.bin`` will be linked
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with the application image directly, forming a single monolithic image.
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Resources
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*********
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- `EVK-IRIS-W1 Website <https://www.u-blox.com/en/product/evk-iris-w1>`_
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- `EVK-IRIS-W1 GitHub <https://github.com/u-blox/u-blox-sho-OpenCPU/tree/master/MCUXpresso/IRIS-W1>`_
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- `EVK-IRIS-W1 User Guide <https://content.u-blox.com/sites/default/files/documents/EVK-IRIS-W1_UserGuide_UBX-23007837.pdf>`_
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BIN
boards/u-blox/ubx_evk_iris_w1/doc/ubx_evk_iris_w1.webp
Normal file
BIN
boards/u-blox/ubx_evk_iris_w1/doc/ubx_evk_iris_w1.webp
Normal file
Binary file not shown.
After Width: | Height: | Size: 69 KiB |
84
boards/u-blox/ubx_evk_iris_w1/fidelex_flash_config.c
Normal file
84
boards/u-blox/ubx_evk_iris_w1/fidelex_flash_config.c
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/*
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* Copyright (c) 2021-2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <flash_config.h>
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__attribute__((section(".flash_conf"), used))
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const fc_flexspi_nor_config_t flexspi_config = {
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.memConfig = {
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.tag = FC_BLOCK_TAG,
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.version = FC_BLOCK_VERSION,
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.readSampleClkSrc = 1,
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.csHoldTime = 3,
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.csSetupTime = 3,
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.deviceModeCfgEnable = 1,
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.deviceModeSeq = { .seqNum = 1, .seqId = 2 },
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.deviceModeArg = 0x0200,
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.configCmdEnable = 0,
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.deviceType = 0x1,
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.sflashPadType = kSerialFlash_4Pads,
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.serialClkFreq = 7,
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.sflashA1Size = 0x1000000U,
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.sflashA2Size = 0,
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.sflashB1Size = 0,
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.sflashB2Size = 0,
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.lookupTable = {
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/* Read */
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[0] = FC_FLEXSPI_LUT_SEQ(
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FC_CMD_SDR, FC_FLEXSPI_1PAD, 0xEB,
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FC_RADDR_SDR, FC_FLEXSPI_4PAD, 0x18),
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[1] = FC_FLEXSPI_LUT_SEQ(
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FC_MODE8_SDR, FC_FLEXSPI_4PAD, 0x00,
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FC_DUMMY_SDR, FC_FLEXSPI_4PAD, 0x04),
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[2] = FC_FLEXSPI_LUT_SEQ(
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FC_READ_SDR, FC_FLEXSPI_4PAD, 0x04,
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FC_STOP_EXE, FC_FLEXSPI_1PAD, 0x00),
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/* Read Status */
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[4 * 1 + 0] = FC_FLEXSPI_LUT_SEQ(
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FC_CMD_SDR, FC_FLEXSPI_1PAD, 0x05,
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FC_READ_SDR, FC_FLEXSPI_1PAD, 0x04),
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/* Write Status */
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[4 * 2 + 0] = FC_FLEXSPI_LUT_SEQ(
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FC_CMD_SDR, FC_FLEXSPI_1PAD, 0x01,
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FC_WRITE_SDR, FC_FLEXSPI_1PAD, 0x02),
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/* Write Enable */
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[4 * 3 + 0] = FC_FLEXSPI_LUT_SEQ(
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FC_CMD_SDR, FC_FLEXSPI_1PAD, 0x06,
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FC_STOP_EXE, FC_FLEXSPI_1PAD, 0x00),
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/* Sector erase */
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[4 * 5 + 0] = FC_FLEXSPI_LUT_SEQ(
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FC_CMD_SDR, FC_FLEXSPI_1PAD, 0x20,
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FC_RADDR_SDR, FC_FLEXSPI_1PAD, 0x18),
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/* Block erase */
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[4 * 8 + 0] = FC_FLEXSPI_LUT_SEQ(
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FC_CMD_SDR, FC_FLEXSPI_1PAD, 0x52,
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FC_RADDR_SDR, FC_FLEXSPI_1PAD, 0x18),
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/* Page program */
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[4 * 9 + 0] = FC_FLEXSPI_LUT_SEQ(
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FC_CMD_SDR, FC_FLEXSPI_1PAD, 0x02,
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FC_RADDR_SDR, FC_FLEXSPI_1PAD, 0x18),
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[4 * 9 + 1] = FC_FLEXSPI_LUT_SEQ(
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FC_WRITE_SDR, FC_FLEXSPI_1PAD, 0x00,
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FC_STOP_EXE, FC_FLEXSPI_1PAD, 0x00),
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/* Chip erase */
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[4 * 11 + 0] = FC_FLEXSPI_LUT_SEQ(
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FC_CMD_SDR, FC_FLEXSPI_1PAD, 0x60,
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FC_STOP_EXE, FC_FLEXSPI_1PAD, 0x00),
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},
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},
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.pageSize = 0x100,
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.sectorSize = 0x1000,
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.ipcmdSerialClkFreq = 0,
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.blockSize = 0x8000,
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.fcb_fill[0] = 0xFFFFFFFFU,
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};
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118
boards/u-blox/ubx_evk_iris_w1/macronix_flash_config.c
Normal file
118
boards/u-blox/ubx_evk_iris_w1/macronix_flash_config.c
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/*
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* Copyright 2021-2024 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <flash_config.h>
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__attribute__((section(".flash_conf"), used))
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const fc_flexspi_nor_config_t flexspi_config = {
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.memConfig = {
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.tag = FC_BLOCK_TAG,
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.version = FC_BLOCK_VERSION,
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.readSampleClkSrc = 1,
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.csHoldTime = 3,
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.csSetupTime = 3,
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.deviceModeCfgEnable = 1,
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.deviceModeSeq = {
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.seqNum = 1,
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.seqId = 2,
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},
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.deviceModeArg = 0x0200,
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.configCmdEnable = 0,
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.deviceType = 0x1,
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.sflashPadType = kSerialFlash_4Pads,
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.serialClkFreq = 7,
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.sflashA1Size = 0x1000000U,
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.sflashA2Size = 0,
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.sflashB1Size = 0,
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.sflashB2Size = 0,
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.lookupTable = {
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/* Read */
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[0] = FC_FLEXSPI_LUT_SEQ(
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||||||
|
FC_CMD_SDR, FC_FLEXSPI_1PAD,
|
||||||
|
0xEB, FC_RADDR_SDR,
|
||||||
|
FC_FLEXSPI_4PAD, 0x18),
|
||||||
|
[1] = FC_FLEXSPI_LUT_SEQ(
|
||||||
|
FC_MODE8_SDR,
|
||||||
|
FC_FLEXSPI_4PAD, 0x00,
|
||||||
|
FC_DUMMY_SDR,
|
||||||
|
FC_FLEXSPI_4PAD, 0x04),
|
||||||
|
[2] = FC_FLEXSPI_LUT_SEQ(
|
||||||
|
FC_READ_SDR,
|
||||||
|
FC_FLEXSPI_4PAD, 0x04,
|
||||||
|
FC_STOP_EXE,
|
||||||
|
FC_FLEXSPI_1PAD, 0x00),
|
||||||
|
|
||||||
|
/* Read Status */
|
||||||
|
[4 * 1 + 0] = FC_FLEXSPI_LUT_SEQ(
|
||||||
|
FC_CMD_SDR,
|
||||||
|
FC_FLEXSPI_1PAD,
|
||||||
|
0x05, FC_READ_SDR,
|
||||||
|
FC_FLEXSPI_1PAD,
|
||||||
|
0x04),
|
||||||
|
|
||||||
|
/* Write Status */
|
||||||
|
[4 * 2 + 0] = FC_FLEXSPI_LUT_SEQ(
|
||||||
|
FC_CMD_SDR,
|
||||||
|
FC_FLEXSPI_1PAD,
|
||||||
|
0x01, FC_WRITE_SDR,
|
||||||
|
FC_FLEXSPI_1PAD,
|
||||||
|
0x02),
|
||||||
|
|
||||||
|
/* Write Enable */
|
||||||
|
[4 * 3 + 0] = FC_FLEXSPI_LUT_SEQ(
|
||||||
|
FC_CMD_SDR,
|
||||||
|
FC_FLEXSPI_1PAD,
|
||||||
|
0x06, FC_STOP_EXE,
|
||||||
|
FC_FLEXSPI_1PAD,
|
||||||
|
0x00),
|
||||||
|
|
||||||
|
/* Sector erase */
|
||||||
|
[4 * 5 + 0] = FC_FLEXSPI_LUT_SEQ(
|
||||||
|
FC_CMD_SDR,
|
||||||
|
FC_FLEXSPI_1PAD,
|
||||||
|
0x20, FC_RADDR_SDR,
|
||||||
|
FC_FLEXSPI_1PAD,
|
||||||
|
0x18),
|
||||||
|
|
||||||
|
/* Block erase */
|
||||||
|
[4 * 8 + 0] = FC_FLEXSPI_LUT_SEQ(
|
||||||
|
FC_CMD_SDR,
|
||||||
|
FC_FLEXSPI_1PAD,
|
||||||
|
0x52, FC_RADDR_SDR,
|
||||||
|
FC_FLEXSPI_1PAD,
|
||||||
|
0x18),
|
||||||
|
|
||||||
|
/* Page program */
|
||||||
|
[4 * 9 + 0] = FC_FLEXSPI_LUT_SEQ(
|
||||||
|
FC_CMD_SDR,
|
||||||
|
FC_FLEXSPI_1PAD,
|
||||||
|
0x02, FC_RADDR_SDR,
|
||||||
|
FC_FLEXSPI_1PAD,
|
||||||
|
0x18),
|
||||||
|
[4 * 9 + 1] = FC_FLEXSPI_LUT_SEQ(
|
||||||
|
FC_WRITE_SDR,
|
||||||
|
FC_FLEXSPI_1PAD,
|
||||||
|
0x00,
|
||||||
|
FC_STOP_EXE,
|
||||||
|
FC_FLEXSPI_1PAD,
|
||||||
|
0x00),
|
||||||
|
|
||||||
|
/* Chip erase */
|
||||||
|
[4 * 11 + 0] = FC_FLEXSPI_LUT_SEQ(
|
||||||
|
FC_CMD_SDR,
|
||||||
|
FC_FLEXSPI_1PAD,
|
||||||
|
0x60, FC_STOP_EXE,
|
||||||
|
FC_FLEXSPI_1PAD,
|
||||||
|
0x00),
|
||||||
|
},
|
||||||
|
},
|
||||||
|
.pageSize = 0x100,
|
||||||
|
.sectorSize = 0x1000,
|
||||||
|
.ipcmdSerialClkFreq = 0,
|
||||||
|
.blockSize = 0x8000,
|
||||||
|
.fcb_fill = 0xFFFFFFFFU,
|
||||||
|
};
|
5
boards/u-blox/ubx_evk_iris_w1/pre_dt_board.cmake
Normal file
5
boards/u-blox/ubx_evk_iris_w1/pre_dt_board.cmake
Normal file
|
@ -0,0 +1,5 @@
|
||||||
|
# Copyright 2023 NXP
|
||||||
|
# SPDX-License-Identifier: Apache-2.0
|
||||||
|
|
||||||
|
# Suppress "spi_bus_bridge" as flexcomm node can be used as a SPI device.
|
||||||
|
list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge")
|
14
boards/u-blox/ubx_evk_iris_w1/revision.cmake
Normal file
14
boards/u-blox/ubx_evk_iris_w1/revision.cmake
Normal file
|
@ -0,0 +1,14 @@
|
||||||
|
# Copyright (c) 2025 u-blox AG
|
||||||
|
# SPDX-License-Identifier: Apache-2.0
|
||||||
|
|
||||||
|
if(NOT BOARD_REVISION)
|
||||||
|
set(BOARD_REVISION fidelex CACHE STRING "Board revision")
|
||||||
|
endif()
|
||||||
|
|
||||||
|
# Validate revision
|
||||||
|
if(NOT BOARD_REVISION STREQUAL "macronix" AND NOT BOARD_REVISION STREQUAL "fidelex")
|
||||||
|
message(FATAL_ERROR
|
||||||
|
"Invalid BOARD_REVISION: ${BOARD_REVISION}\n"
|
||||||
|
"Must be one of: macronix, fidelex"
|
||||||
|
)
|
||||||
|
endif()
|
235
boards/u-blox/ubx_evk_iris_w1/ubx_evk_iris_w1_common.dtsi
Normal file
235
boards/u-blox/ubx_evk_iris_w1/ubx_evk_iris_w1_common.dtsi
Normal file
|
@ -0,0 +1,235 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2025 u-blox AG
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "ubx_evk_iris_w1_rw612-pinctrl.dtsi"
|
||||||
|
#include <zephyr/dt-bindings/input/input-event-codes.h>
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "u-blox evk_iris_w1 rw612";
|
||||||
|
compatible = "u-blox,ubx_evk_iris_w1_rw612";
|
||||||
|
|
||||||
|
aliases {
|
||||||
|
led0 = &rgb_red;
|
||||||
|
led1 = &rgb_green;
|
||||||
|
led2 = &rgb_blue;
|
||||||
|
sw0 = &user_button_0;
|
||||||
|
sw1 = &user_button_1;
|
||||||
|
watchdog0 = &wwdt;
|
||||||
|
usart-0 = &flexcomm3;
|
||||||
|
i2c-0 = &flexcomm2;
|
||||||
|
pwm-0 = &sctimer;
|
||||||
|
};
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
zephyr,sram = &sram_data;
|
||||||
|
zephyr,flash = &w25q512jvfiq;
|
||||||
|
zephyr,console = &flexcomm3;
|
||||||
|
zephyr,shell-uart = &flexcomm3;
|
||||||
|
zephyr,flash-controller = &w25q512jvfiq;
|
||||||
|
zephyr,code-partition = &slot0_partition;
|
||||||
|
zephyr,uart-mcumgr = &flexcomm3;
|
||||||
|
};
|
||||||
|
|
||||||
|
rgb_leds {
|
||||||
|
compatible = "gpio-leds";
|
||||||
|
|
||||||
|
rgb_blue: led_1 {
|
||||||
|
gpios = <&hsgpio1 0xa GPIO_ACTIVE_LOW>;
|
||||||
|
label = "IRIS RGB_BLUE";
|
||||||
|
};
|
||||||
|
|
||||||
|
rgb_green: led_2 {
|
||||||
|
gpios = <&hsgpio1 0xb GPIO_ACTIVE_LOW>;
|
||||||
|
label = "IRIS RGB_GREEN";
|
||||||
|
};
|
||||||
|
|
||||||
|
rgb_red: led_3 {
|
||||||
|
gpios = <&hsgpio1 0xc GPIO_ACTIVE_LOW>;
|
||||||
|
label = "IRIS RGB_RED";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
sw {
|
||||||
|
compatible = "gpio-keys";
|
||||||
|
|
||||||
|
user_button_0: sw_1 {
|
||||||
|
label = "IRIS SWITCH_1"; /* GPIO45 */
|
||||||
|
gpios = <&hsgpio1 0xd GPIO_ACTIVE_LOW>;
|
||||||
|
zephyr,code = <0x2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
user_button_1: sw_2 {
|
||||||
|
label = "IRIS SWITCH_2"; /* GPIO51 */
|
||||||
|
gpios = <&hsgpio1 0x13 GPIO_ACTIVE_LOW>;
|
||||||
|
zephyr,code = <0x3>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&flexcomm3 {
|
||||||
|
compatible = "nxp,lpc-usart";
|
||||||
|
status = "okay";
|
||||||
|
current-speed = <115200>;
|
||||||
|
pinctrl-0 = <&pinmux_flexcomm3_usart>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
};
|
||||||
|
|
||||||
|
&flexcomm0 {
|
||||||
|
compatible = "nxp,lpc-usart";
|
||||||
|
status = "disabled";
|
||||||
|
current-speed = <115200>;
|
||||||
|
pinctrl-0 = <&pinmux_flexcomm0_usart>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
};
|
||||||
|
|
||||||
|
&hsgpio0 {
|
||||||
|
status = "okay";
|
||||||
|
pinctrl-0 = <&pinmux_hsgpio0>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
};
|
||||||
|
|
||||||
|
&hsgpio1 {
|
||||||
|
status = "okay";
|
||||||
|
pinctrl-0 = <&pinmux_hsgpio1>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
};
|
||||||
|
|
||||||
|
&flexspi {
|
||||||
|
status = "okay";
|
||||||
|
ahb-bufferable;
|
||||||
|
ahb-prefetch;
|
||||||
|
ahb-cacheable;
|
||||||
|
ahb-read-addr-opt;
|
||||||
|
ahb-boundary = "1024";
|
||||||
|
rx-clock-source = <1>;
|
||||||
|
rx-clock-source-b = <1>;
|
||||||
|
|
||||||
|
/* external flash */
|
||||||
|
w25q512jvfiq: w25q512jvfiq@0 {
|
||||||
|
compatible = "nxp,imx-flexspi-nor";
|
||||||
|
reg = <0>;
|
||||||
|
size = <DT_SIZE_M(64 * 8)>;
|
||||||
|
status = "okay";
|
||||||
|
erase-block-size = <4096>;
|
||||||
|
write-block-size = <1>;
|
||||||
|
spi-max-frequency = <104000000>;
|
||||||
|
|
||||||
|
partitions {
|
||||||
|
compatible = "fixed-partitions";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Partition sizes must be aligned
|
||||||
|
* to the flash memory sector size of 4KB.
|
||||||
|
*/
|
||||||
|
boot_partition: partition@0 {
|
||||||
|
label = "mcuboot";
|
||||||
|
reg = <0x00000000 DT_SIZE_K(128)>;
|
||||||
|
};
|
||||||
|
|
||||||
|
slot0_partition: partition@20000 {
|
||||||
|
label = "image-0";
|
||||||
|
reg = <0x00020000 DT_SIZE_M(3)>;
|
||||||
|
};
|
||||||
|
|
||||||
|
slot1_partition: partition@320000 {
|
||||||
|
label = "image-1";
|
||||||
|
reg = <0x00320000 DT_SIZE_M(3)>;
|
||||||
|
};
|
||||||
|
|
||||||
|
storage_partition: partition@620000 {
|
||||||
|
label = "storage";
|
||||||
|
reg = <0x00620000 (DT_SIZE_M(58) - DT_SIZE_K(128))>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
aps6404l: aps6404l@2 {
|
||||||
|
compatible = "nxp,imx-flexspi-aps6404l";
|
||||||
|
/* APS6404L is 8MB, 64MBit pSRAM */
|
||||||
|
size = <DT_SIZE_M(8 * 8)>;
|
||||||
|
reg = <2>;
|
||||||
|
spi-max-frequency = <109000000>;
|
||||||
|
|
||||||
|
/* PSRAM cannot be enabled while board is in default XIP
|
||||||
|
* configuration, as it will conflict with flash chip.
|
||||||
|
*/
|
||||||
|
status = "disabled";
|
||||||
|
cs-interval-unit = <1>;
|
||||||
|
cs-interval = <2>;
|
||||||
|
cs-hold-time = <3>;
|
||||||
|
cs-setup-time = <3>;
|
||||||
|
data-valid-time = <6>;
|
||||||
|
column-space = <0>;
|
||||||
|
ahb-write-wait-unit = <2>;
|
||||||
|
ahb-write-wait-interval = <0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&hci {
|
||||||
|
status = "okay";
|
||||||
|
wakeup-source;
|
||||||
|
};
|
||||||
|
|
||||||
|
&wwdt {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&dma0 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&mrt0_channel0 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&ctimer0 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
/* OS Timer is the wakeup source for PM mode 2 */
|
||||||
|
&os_timer {
|
||||||
|
status = "okay";
|
||||||
|
wakeup-source;
|
||||||
|
deep-sleep-counter = <&rtc_highres>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&systick {
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
&sctimer {
|
||||||
|
status = "okay";
|
||||||
|
pinctrl-0 = <&pinmux_pwm0>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
};
|
||||||
|
|
||||||
|
/* RTC is the wakeup source for PM modes 3,4 */
|
||||||
|
&rtc_highres {
|
||||||
|
status = "okay";
|
||||||
|
wakeup-source;
|
||||||
|
};
|
||||||
|
|
||||||
|
&nbu {
|
||||||
|
status = "okay";
|
||||||
|
wakeup-source;
|
||||||
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* the default resistors on the board breaks out the MOSI/MISO
|
||||||
|
* pins to the nets labelled "UART" which go to J1 2 and 4,
|
||||||
|
* but we are using it for spi mosi and miso here.
|
||||||
|
* SCK is on J2 6 as labelled.
|
||||||
|
*/
|
||||||
|
&flexcomm1 {
|
||||||
|
compatible = "nxp,lpc-spi";
|
||||||
|
pinctrl-0 = <&pinmux_flexcomm1_spi>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
status = "okay";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
};
|
|
@ -0,0 +1,89 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2025 u-blox AG
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <nxp/rw/RW612-pinctrl.h>
|
||||||
|
|
||||||
|
&pinctrl {
|
||||||
|
|
||||||
|
// default-UART
|
||||||
|
pinmux_flexcomm3_usart: pinmux_flexcomm3_usart {
|
||||||
|
group0 {
|
||||||
|
pinmux = <IO_MUX_FC3_USART_DATA>;
|
||||||
|
slew-rate = "normal";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
// FCx all default configure as a UART
|
||||||
|
pinmux_flexcomm0_usart: pinmux_flexcomm0_usart {
|
||||||
|
group0 {
|
||||||
|
pinmux = <IO_MUX_FC0_USART_DATA>;
|
||||||
|
slew-rate = "normal";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pinmux_flexcomm2_usart: pinmux_flexcomm2_usart {
|
||||||
|
group0 {
|
||||||
|
pinmux = <IO_MUX_FC2_USART_DATA>;
|
||||||
|
slew-rate = "normal";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pinmux_flexcomm14_usart: pinmux_flexcomm14_usart {
|
||||||
|
group0 {
|
||||||
|
pinmux = <IO_MUX_FC14_USART_DATA>;
|
||||||
|
slew-rate = "normal";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
// i2c
|
||||||
|
pinmux_flexcomm2_i2c: pinmux_flexcomm2_i2c {
|
||||||
|
group0 {
|
||||||
|
pinmux = <IO_MUX_FC2_I2C_16_17>;
|
||||||
|
slew-rate = "normal";
|
||||||
|
bias-pull-up;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
// spi
|
||||||
|
pinmux_flexcomm0_spi: pinmux_flexcomm0_spi {
|
||||||
|
group0 {
|
||||||
|
pinmux = <IO_MUX_FC0_SPI_SS0>;
|
||||||
|
slew-rate = "ultra";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pinmux_flexcomm1_spi: pinmux_flexcomm1_spi {
|
||||||
|
group0 {
|
||||||
|
pinmux = <IO_MUX_FC1_SPI_SS0>;
|
||||||
|
slew-rate = "ultra";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pinmux_pwm0: pinmux_pwm0 {
|
||||||
|
group0 {
|
||||||
|
pinmux = <IO_MUX_SCT_OUT_0>;
|
||||||
|
slew-rate = "normal";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pinmux_hsgpio0: pinmux_hsgpio0 {
|
||||||
|
group0 {
|
||||||
|
pinmux = <IO_MUX_GPIO11
|
||||||
|
IO_MUX_GPIO12
|
||||||
|
IO_MUX_GPIO18
|
||||||
|
IO_MUX_GPIO21>;
|
||||||
|
slew-rate = "normal";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pinmux_hsgpio1: pinmux_hsgpio1 {
|
||||||
|
group0 {
|
||||||
|
pinmux = <IO_MUX_GPIO44
|
||||||
|
IO_MUX_GPIO55>;
|
||||||
|
slew-rate = "normal";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
10
boards/u-blox/ubx_evk_iris_w1/ubx_evk_iris_w1_rw612.dts
Normal file
10
boards/u-blox/ubx_evk_iris_w1/ubx_evk_iris_w1_rw612.dts
Normal file
|
@ -0,0 +1,10 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2025 u-blox AG
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
#include <nxp/nxp_rw6xx.dtsi>
|
||||||
|
#include "ubx_evk_iris_w1_common.dtsi"
|
24
boards/u-blox/ubx_evk_iris_w1/ubx_evk_iris_w1_rw612.yaml
Normal file
24
boards/u-blox/ubx_evk_iris_w1/ubx_evk_iris_w1_rw612.yaml
Normal file
|
@ -0,0 +1,24 @@
|
||||||
|
#
|
||||||
|
# Copyright 2022-2025 NXP
|
||||||
|
# Copyright (c) 2025 u-blox AG
|
||||||
|
# SPDX-License-Identifier: Apache-2.0
|
||||||
|
#
|
||||||
|
|
||||||
|
identifier: ubx_evk_iris_w1/rw612
|
||||||
|
name: EVK-IRIS-W1-RW612
|
||||||
|
type: mcu
|
||||||
|
arch: arm
|
||||||
|
toolchain:
|
||||||
|
- zephyr
|
||||||
|
- gnuarmemb
|
||||||
|
ram: 960
|
||||||
|
flash: 65536
|
||||||
|
supported:
|
||||||
|
- gpio
|
||||||
|
- i2c
|
||||||
|
- spi
|
||||||
|
- dma
|
||||||
|
- watchdog
|
||||||
|
- pwm
|
||||||
|
- hwinfo
|
||||||
|
vendor: u-blox
|
|
@ -0,0 +1,13 @@
|
||||||
|
#
|
||||||
|
# Copyright (c) 2025 u-blox AG
|
||||||
|
# SPDX-License-Identifier: Apache-2.0
|
||||||
|
#
|
||||||
|
|
||||||
|
CONFIG_CONSOLE=y
|
||||||
|
CONFIG_UART_CONSOLE=y
|
||||||
|
CONFIG_SERIAL=y
|
||||||
|
CONFIG_UART_INTERRUPT_DRIVEN=y
|
||||||
|
CONFIG_GPIO=y
|
||||||
|
CONFIG_ARM_MPU=y
|
||||||
|
CONFIG_HW_STACK_PROTECTION=y
|
||||||
|
CONFIG_TRUSTED_EXECUTION_SECURE=y
|
|
@ -0,0 +1,12 @@
|
||||||
|
#
|
||||||
|
# Copyright (c) 2025 u-blox AG
|
||||||
|
# SPDX-License-Identifier: Apache-2.0
|
||||||
|
#
|
||||||
|
CONFIG_CONSOLE=y
|
||||||
|
CONFIG_UART_CONSOLE=y
|
||||||
|
CONFIG_SERIAL=y
|
||||||
|
CONFIG_UART_INTERRUPT_DRIVEN=y
|
||||||
|
CONFIG_GPIO=y
|
||||||
|
CONFIG_ARM_MPU=y
|
||||||
|
CONFIG_HW_STACK_PROTECTION=y
|
||||||
|
CONFIG_TRUSTED_EXECUTION_SECURE=y
|
Loading…
Add table
Add a link
Reference in a new issue