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boards: nxp_rw612: Add support for u-blox EVK-IRIS-W1x

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Add basic board definition of the u-blox EVK-IRIS-W1-rw612 board.
Adds maintainer info for u-blox boards.

Signed-off-by: Tarang Patel <tarang3399.patel@gmail.com>
This commit is contained in:
Tarang Patel 2025-05-21 13:40:17 +00:00 • committed by Dan Kalowsky
commit d2a5c1ca82
18 changed files with 811 additions and 0 deletions
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9
MAINTAINERS.yml
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@ -4669,6 +4669,15 @@ Tracing:
tests:
- tracing
u-blox Platforms:
status: maintained
maintainers:
- 3rang
files:
- boards/u-blox/
labels:
- "platform: u-blox"
USB:
status: maintained
maintainers:

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boards/u-blox/ubx_evk_iris_w1/CMakeLists.txt Normal file
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#
#Copyright 2022-2025 NXP
#Copyright(c)2025 u-blox AG
#SPDX-License-Identifier:Apache-2.0
#
if(CONFIG_NXP_RW6XX_BOOT_HEADER)
zephyr_compile_definitions(BOARD_FLASH_SIZE=${CONFIG_FLASH_SIZE}*1024)
if(BOARD_REVISION STREQUAL "macronix")
zephyr_library_sources(macronix_flash_config.c)
elseif(BOARD_REVISION STREQUAL "fidelex")
zephyr_library_sources(fidelex_flash_config.c)
else()
message(FATAL_ERROR "Unsupported board revision: ${BOARD_REVISION}")
endif()
if(CONFIG_DT_HAS_NXP_ENET_MAC_ENABLED AND CONFIG_XTAL32K)
message(FATAL_ERROR
"Ethernet and external 32K clock source are "
"mutually exclusive on FRDM_RW612 due to shared PCB nets "
"between the ethernet PHY and the external oscillator")
endif()
endif()

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boards/u-blox/ubx_evk_iris_w1/Kconfig.defconfig Normal file
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# SPDX-License-Identifier: Apache-2.0
# Copyright 2022-2025 NXP
# Copyright (c) 2025 u-blox AG
#
if BOARD_UBX_EVK_IRIS_W1
if COUNTER_MCUX_LPC_RTC_1HZ
config XTAL32K
default y
endif # COUNTER_MCUX_LPC_RTC_1HZ
endif # BOARD_UBX_EVK_IRIS_W1

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boards/u-blox/ubx_evk_iris_w1/Kconfig.ubx_evk_iris_w1 Normal file
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# EVK-IRIS-W1 board configuration
# Copyright (c) 2025 u-blox AG
# SPDX-License-Identifier: Apache-2.0
config BOARD_UBX_EVK_IRIS_W1
select SOC_PART_NUMBER_RW612ETA2I

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boards/u-blox/ubx_evk_iris_w1/board.cmake Normal file
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# Copyright 2022-2023 NXP
# SPDX-License-Identifier: Apache-2.0
board_runner_args(jlink "--device=RW612" "--reset-after-load")
board_runner_args(linkserver "--device=RW612:RDRW612")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)

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boards/u-blox/ubx_evk_iris_w1/board.yml Normal file
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board:
name: ubx_evk_iris_w1
full_name: EVK-IRIS-W106-RW612
vendor: u-blox
revision:
format: custom
default: fidelex
revisions:
- name: "macronix"
- name: "fidelex"
socs:
- name: rw612

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.. zephyr:board:: ubx_evk_iris_w1
Overview
********
The EVK-IRIS-W10x evaluation kit enables stand-alone use of the IRIS-W10 series module. This guide
provides details about the hardware functionality of the EVK-IRIS-W10 board and includes setup
instructions for starting development.
All pins and interfaces supported on IRIS-W10 series modules are easily accessible from the
evaluation board. Simple USB connections serve as the physical interfaces for power, programming
COM ports, debugging, and USB peripheral connectors. Additionally, the board features other
interfaces like Ethernet RJ45 and an SDIO header. The EVK-IRIS-W10 board is equipped with a Reset
button, Boot button, and two user-configurable buttons. Current sense resistors are incorporated for
accurate current measurement within the module.
For flexible use, GPIO signals are accessible through headers and are complemented by four
mikroBUS™ standard slots for convenient utilization of Click boards™. Each Click board can be
seamlessly plugged into an available mikroBUS™ slot to facilitate effortless hardware expansion with
a variety of standardized compact add-on boards. Click boards are designed to accommodate a
diverse range of electronic modules, including sensors, transceivers, displays, encoders, motor
drivers, connection ports, and more. For further information about the Click boards, visit the MIKROE
website.
Hardware
********
- 260 MHz ARM Cortex-M33, tri-radio cores for Wi-Fi 6 + BLE 5.3 + 802.15.4
- 1.2 MB on-chip SRAM
- EVK-IRIS-W101 evaluation board with IRIS-W101 module. Dual-band PCB antenna for WLAN
with 100 mm coaxial cable and U.FL connector
- EVK-IRIS-W106 evaluation board with IRIS-W106 module. Dual-band integrated PCB trace
antenna (external antenna not supplied)
Flash Memory Configuration
==========================
The IRIS-W1 board uses different flash vendors depending on revision:
- ``@macronix``: Module build up to 2023 week 45
- ``@fidelex``: Module build 2023 week 46 (2346) onward
To build for a specific flash version:
.. code-block:: bash
west build -b ubx_evk_iris_w1@macronix
west build -b ubx_evk_iris_w1@fidelex
Supported Features
==================
.. zephyr:board-supported-hw::
Basic functionality like UART (default on FC3), GPIOs (I²C, SPI), and the on-board RGB LEDs is supported.
Programming and Debugging
*************************
.. zephyr:board-supported-runners::
Configuring a Debug Probe
=========================
A debug probe is used for both flashing and debugging the board. This board is
configured by default to use the J-Link firmware.
Configuring a Console
=====================
Connect a USB cable from your PC to USB3, and use the serial terminal of your choice
(minicom, PuTTY, etc.) with the following settings:
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Flashing
========
Here is an example for the ``hello_world`` application.
Open a serial terminal, reset the board (press the RESET button), and you should
see the following message in the terminal:
.. code-block:: console
**** Booting Zephyr OS build v4.1.0-2794-g6463c68bc394 ****
Hello World ! ubx_evk_iris_w1/rw612
Wireless Connectivity Support
*****************************
Fetch Binary Blobs
==================
To support Bluetooth or Wi-Fi, ``ubx_evk_iris_w1`` requires fetching binary blobs. This can be
achieved by running the following command:
.. code-block:: console
west blobs fetch hal_nxp
Bluetooth
=========
BLE functionality requires fetching binary blobs, so make sure to follow
the "Fetch Binary Blobs" section first.
The required binary blob
``<zephyr workspace>/modules/hal/nxp/zephyr/blobs/rw61x_sb_ble_a2.bin`` will be linked
with the application image directly, forming a single monolithic image.
Wi-Fi
=====
Wi-Fi functionality also requires fetching binary blobs, so make sure to follow
the "Fetch Binary Blobs" section first.
The required binary blob
``<zephyr workspace>/modules/hal/nxp/zephyr/blobs/rw61x_sb_wifi_a2.bin`` will be linked
with the application image directly, forming a single monolithic image.
Resources
*********
- `EVK-IRIS-W1 Website <https://www.u-blox.com/en/product/evk-iris-w1>`_
- `EVK-IRIS-W1 GitHub <https://github.com/u-blox/u-blox-sho-OpenCPU/tree/master/MCUXpresso/IRIS-W1>`_
- `EVK-IRIS-W1 User Guide <https://content.u-blox.com/sites/default/files/documents/EVK-IRIS-W1_UserGuide_UBX-23007837.pdf>`_

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boards/u-blox/ubx_evk_iris_w1/fidelex_flash_config.c Normal file
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/*
* Copyright (c) 2021-2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <flash_config.h>
__attribute__((section(".flash_conf"), used))
const fc_flexspi_nor_config_t flexspi_config = {
.memConfig = {
.tag = FC_BLOCK_TAG,
.version = FC_BLOCK_VERSION,
.readSampleClkSrc = 1,
.csHoldTime = 3,
.csSetupTime = 3,
.deviceModeCfgEnable = 1,
.deviceModeSeq = { .seqNum = 1, .seqId = 2 },
.deviceModeArg = 0x0200,
.configCmdEnable = 0,
.deviceType = 0x1,
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = 7,
.sflashA1Size = 0x1000000U,
.sflashA2Size = 0,
.sflashB1Size = 0,
.sflashB2Size = 0,
.lookupTable = {
/* Read */
[0] = FC_FLEXSPI_LUT_SEQ(
FC_CMD_SDR, FC_FLEXSPI_1PAD, 0xEB,
FC_RADDR_SDR, FC_FLEXSPI_4PAD, 0x18),
[1] = FC_FLEXSPI_LUT_SEQ(
FC_MODE8_SDR, FC_FLEXSPI_4PAD, 0x00,
FC_DUMMY_SDR, FC_FLEXSPI_4PAD, 0x04),
[2] = FC_FLEXSPI_LUT_SEQ(
FC_READ_SDR, FC_FLEXSPI_4PAD, 0x04,
FC_STOP_EXE, FC_FLEXSPI_1PAD, 0x00),
/* Read Status */
[4 * 1 + 0] = FC_FLEXSPI_LUT_SEQ(
FC_CMD_SDR, FC_FLEXSPI_1PAD, 0x05,
FC_READ_SDR, FC_FLEXSPI_1PAD, 0x04),
/* Write Status */
[4 * 2 + 0] = FC_FLEXSPI_LUT_SEQ(
FC_CMD_SDR, FC_FLEXSPI_1PAD, 0x01,
FC_WRITE_SDR, FC_FLEXSPI_1PAD, 0x02),
/* Write Enable */
[4 * 3 + 0] = FC_FLEXSPI_LUT_SEQ(
FC_CMD_SDR, FC_FLEXSPI_1PAD, 0x06,
FC_STOP_EXE, FC_FLEXSPI_1PAD, 0x00),
/* Sector erase */
[4 * 5 + 0] = FC_FLEXSPI_LUT_SEQ(
FC_CMD_SDR, FC_FLEXSPI_1PAD, 0x20,
FC_RADDR_SDR, FC_FLEXSPI_1PAD, 0x18),
/* Block erase */
[4 * 8 + 0] = FC_FLEXSPI_LUT_SEQ(
FC_CMD_SDR, FC_FLEXSPI_1PAD, 0x52,
FC_RADDR_SDR, FC_FLEXSPI_1PAD, 0x18),
/* Page program */
[4 * 9 + 0] = FC_FLEXSPI_LUT_SEQ(
FC_CMD_SDR, FC_FLEXSPI_1PAD, 0x02,
FC_RADDR_SDR, FC_FLEXSPI_1PAD, 0x18),
[4 * 9 + 1] = FC_FLEXSPI_LUT_SEQ(
FC_WRITE_SDR, FC_FLEXSPI_1PAD, 0x00,
FC_STOP_EXE, FC_FLEXSPI_1PAD, 0x00),
/* Chip erase */
[4 * 11 + 0] = FC_FLEXSPI_LUT_SEQ(
FC_CMD_SDR, FC_FLEXSPI_1PAD, 0x60,
FC_STOP_EXE, FC_FLEXSPI_1PAD, 0x00),
},
},
.pageSize = 0x100,
.sectorSize = 0x1000,
.ipcmdSerialClkFreq = 0,
.blockSize = 0x8000,
.fcb_fill[0] = 0xFFFFFFFFU,
};

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boards/u-blox/ubx_evk_iris_w1/macronix_flash_config.c Normal file
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/*
* Copyright 2021-2024 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <flash_config.h>
__attribute__((section(".flash_conf"), used))
const fc_flexspi_nor_config_t flexspi_config = {
.memConfig = {
.tag = FC_BLOCK_TAG,
.version = FC_BLOCK_VERSION,
.readSampleClkSrc = 1,
.csHoldTime = 3,
.csSetupTime = 3,
.deviceModeCfgEnable = 1,
.deviceModeSeq = {
.seqNum = 1,
.seqId = 2,
},
.deviceModeArg = 0x0200,
.configCmdEnable = 0,
.deviceType = 0x1,
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = 7,
.sflashA1Size = 0x1000000U,
.sflashA2Size = 0,
.sflashB1Size = 0,
.sflashB2Size = 0,
.lookupTable = {
/* Read */
[0] = FC_FLEXSPI_LUT_SEQ(
FC_CMD_SDR, FC_FLEXSPI_1PAD,
0xEB, FC_RADDR_SDR,
FC_FLEXSPI_4PAD, 0x18),
[1] = FC_FLEXSPI_LUT_SEQ(
FC_MODE8_SDR,
FC_FLEXSPI_4PAD, 0x00,
FC_DUMMY_SDR,
FC_FLEXSPI_4PAD, 0x04),
[2] = FC_FLEXSPI_LUT_SEQ(
FC_READ_SDR,
FC_FLEXSPI_4PAD, 0x04,
FC_STOP_EXE,
FC_FLEXSPI_1PAD, 0x00),
/* Read Status */
[4 * 1 + 0] = FC_FLEXSPI_LUT_SEQ(
FC_CMD_SDR,
FC_FLEXSPI_1PAD,
0x05, FC_READ_SDR,
FC_FLEXSPI_1PAD,
0x04),
/* Write Status */
[4 * 2 + 0] = FC_FLEXSPI_LUT_SEQ(
FC_CMD_SDR,
FC_FLEXSPI_1PAD,
0x01, FC_WRITE_SDR,
FC_FLEXSPI_1PAD,
0x02),
/* Write Enable */
[4 * 3 + 0] = FC_FLEXSPI_LUT_SEQ(
FC_CMD_SDR,
FC_FLEXSPI_1PAD,
0x06, FC_STOP_EXE,
FC_FLEXSPI_1PAD,
0x00),
/* Sector erase */
[4 * 5 + 0] = FC_FLEXSPI_LUT_SEQ(
FC_CMD_SDR,
FC_FLEXSPI_1PAD,
0x20, FC_RADDR_SDR,
FC_FLEXSPI_1PAD,
0x18),
/* Block erase */
[4 * 8 + 0] = FC_FLEXSPI_LUT_SEQ(
FC_CMD_SDR,
FC_FLEXSPI_1PAD,
0x52, FC_RADDR_SDR,
FC_FLEXSPI_1PAD,
0x18),
/* Page program */
[4 * 9 + 0] = FC_FLEXSPI_LUT_SEQ(
FC_CMD_SDR,
FC_FLEXSPI_1PAD,
0x02, FC_RADDR_SDR,
FC_FLEXSPI_1PAD,
0x18),
[4 * 9 + 1] = FC_FLEXSPI_LUT_SEQ(
FC_WRITE_SDR,
FC_FLEXSPI_1PAD,
0x00,
FC_STOP_EXE,
FC_FLEXSPI_1PAD,
0x00),
/* Chip erase */
[4 * 11 + 0] = FC_FLEXSPI_LUT_SEQ(
FC_CMD_SDR,
FC_FLEXSPI_1PAD,
0x60, FC_STOP_EXE,
FC_FLEXSPI_1PAD,
0x00),
},
},
.pageSize = 0x100,
.sectorSize = 0x1000,
.ipcmdSerialClkFreq = 0,
.blockSize = 0x8000,
.fcb_fill = 0xFFFFFFFFU,
};

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# Copyright 2023 NXP
# SPDX-License-Identifier: Apache-2.0
# Suppress "spi_bus_bridge" as flexcomm node can be used as a SPI device.
list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge")

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# Copyright (c) 2025 u-blox AG
# SPDX-License-Identifier: Apache-2.0
if(NOT BOARD_REVISION)
set(BOARD_REVISION fidelex CACHE STRING "Board revision")
endif()
# Validate revision
if(NOT BOARD_REVISION STREQUAL "macronix" AND NOT BOARD_REVISION STREQUAL "fidelex")
message(FATAL_ERROR
"Invalid BOARD_REVISION: ${BOARD_REVISION}\n"
"Must be one of: macronix, fidelex"
)
endif()

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/*
* Copyright (c) 2025 u-blox AG
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "ubx_evk_iris_w1_rw612-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "u-blox evk_iris_w1 rw612";
compatible = "u-blox,ubx_evk_iris_w1_rw612";
aliases {
led0 = &rgb_red;
led1 = &rgb_green;
led2 = &rgb_blue;
sw0 = &user_button_0;
sw1 = &user_button_1;
watchdog0 = &wwdt;
usart-0 = &flexcomm3;
i2c-0 = &flexcomm2;
pwm-0 = &sctimer;
};
chosen {
zephyr,sram = &sram_data;
zephyr,flash = &w25q512jvfiq;
zephyr,console = &flexcomm3;
zephyr,shell-uart = &flexcomm3;
zephyr,flash-controller = &w25q512jvfiq;
zephyr,code-partition = &slot0_partition;
zephyr,uart-mcumgr = &flexcomm3;
};
rgb_leds {
compatible = "gpio-leds";
rgb_blue: led_1 {
gpios = <&hsgpio1 0xa GPIO_ACTIVE_LOW>;
label = "IRIS RGB_BLUE";
};
rgb_green: led_2 {
gpios = <&hsgpio1 0xb GPIO_ACTIVE_LOW>;
label = "IRIS RGB_GREEN";
};
rgb_red: led_3 {
gpios = <&hsgpio1 0xc GPIO_ACTIVE_LOW>;
label = "IRIS RGB_RED";
};
};
sw {
compatible = "gpio-keys";
user_button_0: sw_1 {
label = "IRIS SWITCH_1"; /* GPIO45 */
gpios = <&hsgpio1 0xd GPIO_ACTIVE_LOW>;
zephyr,code = <0x2>;
};
user_button_1: sw_2 {
label = "IRIS SWITCH_2"; /* GPIO51 */
gpios = <&hsgpio1 0x13 GPIO_ACTIVE_LOW>;
zephyr,code = <0x3>;
};
};
};
&flexcomm3 {
compatible = "nxp,lpc-usart";
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&pinmux_flexcomm3_usart>;
pinctrl-names = "default";
};
&flexcomm0 {
compatible = "nxp,lpc-usart";
status = "disabled";
current-speed = <115200>;
pinctrl-0 = <&pinmux_flexcomm0_usart>;
pinctrl-names = "default";
};
&hsgpio0 {
status = "okay";
pinctrl-0 = <&pinmux_hsgpio0>;
pinctrl-names = "default";
};
&hsgpio1 {
status = "okay";
pinctrl-0 = <&pinmux_hsgpio1>;
pinctrl-names = "default";
};
&flexspi {
status = "okay";
ahb-bufferable;
ahb-prefetch;
ahb-cacheable;
ahb-read-addr-opt;
ahb-boundary = "1024";
rx-clock-source = <1>;
rx-clock-source-b = <1>;
/* external flash */
w25q512jvfiq: w25q512jvfiq@0 {
compatible = "nxp,imx-flexspi-nor";
reg = <0>;
size = <DT_SIZE_M(64 * 8)>;
status = "okay";
erase-block-size = <4096>;
write-block-size = <1>;
spi-max-frequency = <104000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/*
* Partition sizes must be aligned
* to the flash memory sector size of 4KB.
*/
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(128)>;
};
slot0_partition: partition@20000 {
label = "image-0";
reg = <0x00020000 DT_SIZE_M(3)>;
};
slot1_partition: partition@320000 {
label = "image-1";
reg = <0x00320000 DT_SIZE_M(3)>;
};
storage_partition: partition@620000 {
label = "storage";
reg = <0x00620000 (DT_SIZE_M(58) - DT_SIZE_K(128))>;
};
};
};
aps6404l: aps6404l@2 {
compatible = "nxp,imx-flexspi-aps6404l";
/* APS6404L is 8MB, 64MBit pSRAM */
size = <DT_SIZE_M(8 * 8)>;
reg = <2>;
spi-max-frequency = <109000000>;
/* PSRAM cannot be enabled while board is in default XIP
* configuration, as it will conflict with flash chip.
*/
status = "disabled";
cs-interval-unit = <1>;
cs-interval = <2>;
cs-hold-time = <3>;
cs-setup-time = <3>;
data-valid-time = <6>;
column-space = <0>;
ahb-write-wait-unit = <2>;
ahb-write-wait-interval = <0>;
};
};
&hci {
status = "okay";
wakeup-source;
};
&wwdt {
status = "okay";
};
&dma0 {
status = "okay";
};
&mrt0_channel0 {
status = "okay";
};
&ctimer0 {
status = "okay";
};
/* OS Timer is the wakeup source for PM mode 2 */
&os_timer {
status = "okay";
wakeup-source;
deep-sleep-counter = <&rtc_highres>;
};
&systick {
status = "disabled";
};
&sctimer {
status = "okay";
pinctrl-0 = <&pinmux_pwm0>;
pinctrl-names = "default";
};
/* RTC is the wakeup source for PM modes 3,4 */
&rtc_highres {
status = "okay";
wakeup-source;
};
&nbu {
status = "okay";
wakeup-source;
};
/*
* the default resistors on the board breaks out the MOSI/MISO
* pins to the nets labelled "UART" which go to J1 2 and 4,
* but we are using it for spi mosi and miso here.
* SCK is on J2 6 as labelled.
*/
&flexcomm1 {
compatible = "nxp,lpc-spi";
pinctrl-0 = <&pinmux_flexcomm1_spi>;
pinctrl-names = "default";
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
};

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/*
* Copyright (c) 2025 u-blox AG
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <nxp/rw/RW612-pinctrl.h>
&pinctrl {
// default-UART
pinmux_flexcomm3_usart: pinmux_flexcomm3_usart {
group0 {
pinmux = <IO_MUX_FC3_USART_DATA>;
slew-rate = "normal";
};
};
// FCx all default configure as a UART
pinmux_flexcomm0_usart: pinmux_flexcomm0_usart {
group0 {
pinmux = <IO_MUX_FC0_USART_DATA>;
slew-rate = "normal";
};
};
pinmux_flexcomm2_usart: pinmux_flexcomm2_usart {
group0 {
pinmux = <IO_MUX_FC2_USART_DATA>;
slew-rate = "normal";
};
};
pinmux_flexcomm14_usart: pinmux_flexcomm14_usart {
group0 {
pinmux = <IO_MUX_FC14_USART_DATA>;
slew-rate = "normal";
};
};
// i2c
pinmux_flexcomm2_i2c: pinmux_flexcomm2_i2c {
group0 {
pinmux = <IO_MUX_FC2_I2C_16_17>;
slew-rate = "normal";
bias-pull-up;
};
};
// spi
pinmux_flexcomm0_spi: pinmux_flexcomm0_spi {
group0 {
pinmux = <IO_MUX_FC0_SPI_SS0>;
slew-rate = "ultra";
};
};
pinmux_flexcomm1_spi: pinmux_flexcomm1_spi {
group0 {
pinmux = <IO_MUX_FC1_SPI_SS0>;
slew-rate = "ultra";
};
};
pinmux_pwm0: pinmux_pwm0 {
group0 {
pinmux = <IO_MUX_SCT_OUT_0>;
slew-rate = "normal";
};
};
pinmux_hsgpio0: pinmux_hsgpio0 {
group0 {
pinmux = <IO_MUX_GPIO11
IO_MUX_GPIO12
IO_MUX_GPIO18
IO_MUX_GPIO21>;
slew-rate = "normal";
};
};
pinmux_hsgpio1: pinmux_hsgpio1 {
group0 {
pinmux = <IO_MUX_GPIO44
IO_MUX_GPIO55>;
slew-rate = "normal";
};
};
};

10
boards/u-blox/ubx_evk_iris_w1/ubx_evk_iris_w1_rw612.dts Normal file
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/*
* Copyright (c) 2025 u-blox AG
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <nxp/nxp_rw6xx.dtsi>
#include "ubx_evk_iris_w1_common.dtsi"

24
boards/u-blox/ubx_evk_iris_w1/ubx_evk_iris_w1_rw612.yaml Normal file
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#
# Copyright 2022-2025 NXP
# Copyright (c) 2025 u-blox AG
# SPDX-License-Identifier: Apache-2.0
#
identifier: ubx_evk_iris_w1/rw612
name: EVK-IRIS-W1-RW612
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
ram: 960
flash: 65536
supported:
- gpio
- i2c
- spi
- dma
- watchdog
- pwm
- hwinfo
vendor: u-blox

13
boards/u-blox/ubx_evk_iris_w1/ubx_evk_iris_w1_rw612_fidelex_defconfig Normal file
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#
# Copyright (c) 2025 u-blox AG
# SPDX-License-Identifier: Apache-2.0
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_GPIO=y
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y
CONFIG_TRUSTED_EXECUTION_SECURE=y

12
boards/u-blox/ubx_evk_iris_w1/ubx_evk_iris_w1_rw612_macronix_defconfig Normal file
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#
# Copyright (c) 2025 u-blox AG
# SPDX-License-Identifier: Apache-2.0
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_GPIO=y
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y
CONFIG_TRUSTED_EXECUTION_SECURE=y