diff --git a/drivers/timer/riscv_machine_timer.c b/drivers/timer/riscv_machine_timer.c
index 7d63e4e19f0..1584a6dc5a7 100644
--- a/drivers/timer/riscv_machine_timer.c
+++ b/drivers/timer/riscv_machine_timer.c
@@ -21,12 +21,17 @@
 static struct k_spinlock lock;
 static uint64_t last_count;
 
+static uint64_t get_hart_mtimecmp(void)
+{
+	return RISCV_MTIMECMP_BASE + (_current_cpu->id * 8);
+}
+
 static void set_mtimecmp(uint64_t time)
 {
 #ifdef CONFIG_64BIT
-	*(volatile uint64_t *)RISCV_MTIMECMP_BASE = time;
+	*(volatile uint64_t *)get_hart_mtimecmp() = time;
 #else
-	volatile uint32_t *r = (uint32_t *)RISCV_MTIMECMP_BASE;
+	volatile uint32_t *r = (uint32_t *)(uint32_t)get_hart_mtimecmp();
 
 	/* Per spec, the RISC-V MTIME/MTIMECMP registers are 64 bit,
 	 * but are NOT internally latched for multiword transfers.  So
@@ -155,5 +160,13 @@ static int sys_clock_driver_init(const struct device *dev)
 	return 0;
 }
 
+#ifdef CONFIG_SMP
+void smp_timer_init(void)
+{
+	set_mtimecmp(last_count + CYC_PER_TICK);
+	irq_enable(RISCV_MACHINE_TIMER_IRQ);
+}
+#endif
+
 SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
 	 CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);