arm: cmsis: Convert _Scb*FaultIs* & _ScbIs*Fault to use CMSIS register access
Converted: _ScbHardFaultIsBusErrOnVectorRead _ScbIsMemFault _ScbMemFaultIsMmfarValid _ScbMemFaultIsStacking _ScbMemFaultIsUnstacking _ScbMemFaultIsDataAccessViolation _ScbMemFaultIsInstrAccessViolation _ScbIsBusFault _ScbBusFaultIsBfarValid _ScbBusFaultIsStacking _ScbBusFaultIsUnstacking _ScbBusFaultIsImprecise _ScbBusFaultIsPrecise _ScbBusFaultIsInstrBusErr _ScbIsUsageFault _ScbUsageFaultIsDivByZero _ScbUsageFaultIsUnaligned _ScbUsageFaultIsNoCp _ScbUsageFaultIsInvalidPcLoad _ScbUsageFaultIsInvalidState _ScbUsageFaultIsUndefinedInstr To use direct CMSIS register access Jira: ZEP-1568 Change-Id: I2a99a4101c5960f825a502c225e511e49fe93bba Signed-off-by: Kumar Gala <kumar.gala@linaro.org> Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This commit is contained in:
Kumar Gala
Maureen Helm
parent
1a146174cb
commit
d2679c7bbb
3 changed files with 73 additions and 331 deletions
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@ -36,6 +36,55 @@ extern "C" {
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#define CPACR_CP11_RESERVED (2UL << _SCS_CPACR_CP11_Pos)
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#define CPACR_CP11_FULL_ACCESS (3UL << _SCS_CPACR_CP11_Pos)
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#define SCB_UFSR (*((__IOM uint16_t *) &SCB->CFSR + 2))
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#define SCB_BFSR (*((__IOM uint8_t *) &SCB->CFSR + 1))
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#define SCB_MMFSR (*((__IOM uint8_t *) &SCB->CFSR))
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/* CFSR[UFSR] */
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#define CFSR_DIVBYZERO_Pos (25U)
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#define CFSR_DIVBYZERO_Msk (0x1U << CFSR_DIVBYZERO_Pos)
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#define CFSR_UNALIGNED_Pos (24U)
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#define CFSR_UNALIGNED_Msk (0x1U << CFSR_UNALIGNED_Pos)
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#define CFSR_NOCP_Pos (19U)
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#define CFSR_NOCP_Msk (0x1U << CFSR_NOCP_Pos)
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#define CFSR_INVPC_Pos (18U)
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#define CFSR_INVPC_Msk (0x1U << CFSR_INVPC_Pos)
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#define CFSR_INVSTATE_Pos (17U)
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#define CFSR_INVSTATE_Msk (0x1U << CFSR_INVSTATE_Pos)
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#define CFSR_UNDEFINSTR_Pos (16U)
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#define CFSR_UNDEFINSTR_Msk (0x1U << CFSR_UNDEFINSTR_Pos)
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/* CFSR[BFSR] */
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#define CFSR_BFARVALID_Pos (15U)
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#define CFSR_BFARVALID_Msk (0x1U << CFSR_BFARVALID_Pos)
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#define CFSR_LSPERR_Pos (13U)
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#define CFSR_LSPERR_Msk (0x1U << CFSR_LSPERR_Pos)
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#define CFSR_STKERR_Pos (12U)
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#define CFSR_STKERR_Msk (0x1U << CFSR_STKERR_Pos)
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#define CFSR_UNSTKERR_Pos (11U)
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#define CFSR_UNSTKERR_Msk (0x1U << CFSR_UNSTKERR_Pos)
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#define CFSR_IMPRECISERR_Pos (10U)
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#define CFSR_IMPRECISERR_Msk (0x1U << CFSR_IMPRECISERR_Pos)
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#define CFSR_PRECISERR_Pos (9U)
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#define CFSR_PRECISERR_Msk (0x1U << CFSR_PRECISERR_Pos)
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#define CFSR_IBUSERR_Pos (8U)
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#define CFSR_IBUSERR_Msk (0x1U << CFSR_IBUSERR_Pos)
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/* CFSR[MMFSR] */
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#define CFSR_MMARVALID_Pos (7U)
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#define CFSR_MMARVALID_Msk (0x1U << CFSR_MMARVALID_Pos)
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#define CFSR_MLSPERR_Pos (5U)
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#define CFSR_MLSPERR_Msk (0x1U << CFSR_MLSPERR_Pos)
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#define CFSR_MSTKERR_Pos (4U)
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#define CFSR_MSTKERR_Msk (0x1U << CFSR_MSTKERR_Pos)
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#define CFSR_MUNSTKERR_Pos (3U)
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#define CFSR_MUNSTKERR_Msk (0x1U << CFSR_MUNSTKERR_Pos)
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#define CFSR_DACCVIOL_Pos (1U)
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#define CFSR_DACCVIOL_Msk (0x1U << CFSR_DACCVIOL_Pos)
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#define CFSR_IACCVIOL_Pos (0U)
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#define CFSR_IACCVIOL_Msk (0x1U << CFSR_IACCVIOL_Pos)
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/* Fill in CMSIS required values for non-CMSIS compliant SoCs.
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* Use __NVIC_PRIO_BITS as it is required and simple to check, but
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* ultimately all SoCs will define their own CMSIS types and constants.
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@ -46,21 +46,6 @@ extern "C" {
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_ARMV7_M)
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/**
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*
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* @brief Find out if a hard fault is caused by a bus error on vector read
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*
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* This routine determines if a hard fault is caused by a bus error during
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* a vector table read operation.
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*
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* @return 1 if so, 0 otherwise
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*/
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static inline int _ScbHardFaultIsBusErrOnVectorRead(void)
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{
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return __scs.scb.hfsr.bit.vecttbl;
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}
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/**
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*
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* @brief Clear all hard faults (HFSR register)
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@ -75,34 +60,6 @@ static inline int _ScbHardFaultAllFaultsReset(void)
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return __scs.scb.hfsr.val = 0xffff;
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}
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/**
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*
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* @brief Find out if a hard fault is an MPU fault
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*
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* This routine determines if a hard fault is an MPU fault.
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*
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* @return 1 if so, 0 otherwise
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*/
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static inline int _ScbIsMemFault(void)
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{
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return !!__scs.scb.cfsr.byte.mmfsr.val;
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}
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/**
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*
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* @brief Find out if the MMFAR register contains a valid value
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*
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* The MMFAR register contains the faulting address on an MPU fault.
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*
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* @return 1 if so, 0 otherwise
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*/
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static inline int _ScbMemFaultIsMmfarValid(void)
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{
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return !!__scs.scb.cfsr.byte.mmfsr.bit.mmarvalid;
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}
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/**
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*
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* @brief Invalid the value in MMFAR
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@ -132,66 +89,6 @@ static inline void _ScbMemFaultAllFaultsReset(void)
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__scs.scb.cfsr.byte.mmfsr.val = 0xfe;
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}
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/**
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*
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* @brief Find out if an MPU fault is a stacking fault
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*
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* This routine determines if an MPU fault is a stacking fault.
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* This may occur upon exception entry.
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*
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* @return 1 if so, 0 otherwise
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*/
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static inline int _ScbMemFaultIsStacking(void)
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{
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return !!__scs.scb.cfsr.byte.mmfsr.bit.mstkerr;
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}
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/**
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*
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* @brief Find out if an MPU fault is an unstacking fault
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*
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* This routine determines if an MPU fault is an unstacking fault.
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* This may occur upon exception exit.
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*
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* @return 1 if so, 0 otherwise
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*/
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static inline int _ScbMemFaultIsUnstacking(void)
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{
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return !!__scs.scb.cfsr.byte.mmfsr.bit.munstkerr;
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}
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/**
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*
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* @brief Find out if an MPU fault is a data access violation
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*
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* If this routine returns 1, read the MMFAR register via _ScbMemFaultAddrGet()
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* to get the faulting address.
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*
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* @return 1 if so, 0 otherwise
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*/
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static inline int _ScbMemFaultIsDataAccessViolation(void)
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{
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return !!__scs.scb.cfsr.byte.mmfsr.bit.daccviol;
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}
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/**
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*
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* @brief Find out if an MPU fault is an instruction access violation
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*
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* This routine determines if an MPU fault is due to an instruction access
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* violation.
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*
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* @return 1 if so, 0 otherwise
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*/
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static inline int _ScbMemFaultIsInstrAccessViolation(void)
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{
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return !!__scs.scb.cfsr.byte.mmfsr.bit.iaccviol;
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}
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/**
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*
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* @brief Find out the faulting address on an MPU fault
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@ -204,34 +101,6 @@ static inline uint32_t _ScbMemFaultAddrGet(void)
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return __scs.scb.mmfar;
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}
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/**
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*
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* @brief Find out if a hard fault is a bus fault
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*
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* This routine determines if a hard fault is a bus fault.
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*
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* @return 1 if so, 0 otherwise
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*/
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static inline int _ScbIsBusFault(void)
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{
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return !!__scs.scb.cfsr.byte.bfsr.val;
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}
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/**
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*
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* @brief Find out if the BFAR register contains a valid value
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*
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* The BFAR register contains the faulting address on bus fault.
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*
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* @return 1 if so, 0 otherwise
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*/
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static inline int _ScbBusFaultIsBfarValid(void)
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{
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return !!__scs.scb.cfsr.byte.bfsr.bit.bfarvalid;
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}
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/**
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*
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* @brief Invalid the value in BFAR
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@ -261,80 +130,6 @@ static inline void _ScbBusFaultAllFaultsReset(void)
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__scs.scb.cfsr.byte.bfsr.val = 0xfe;
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}
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/**
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*
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* @brief Find out if a bus fault is a stacking fault
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*
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* This routine determines if a bus fault is a stacking fault.
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* This may occurs upon exception entry.
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*
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* @return 1 if so, 0 otherwise
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*/
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static inline int _ScbBusFaultIsStacking(void)
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{
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return !!__scs.scb.cfsr.byte.bfsr.bit.stkerr;
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}
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/**
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*
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* @brief Find out if a bus fault is an unstacking fault
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*
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* This routine determines if a bus fault is an unstacking fault.
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* This may occur upon exception exit.
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*
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* @return 1 if so, 0 otherwise
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*/
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static inline int _ScbBusFaultIsUnstacking(void)
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{
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return !!__scs.scb.cfsr.byte.bfsr.bit.unstkerr;
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}
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/**
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*
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* @brief Find out if a bus fault is an imprecise error
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*
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* This routine determines if a bus fault is an imprecise error.
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*
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* @return 1 if so, 0 otherwise
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*/
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static inline int _ScbBusFaultIsImprecise(void)
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{
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return !!__scs.scb.cfsr.byte.bfsr.bit.impreciserr;
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}
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/**
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*
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* @brief Find out if a bus fault is an precise error
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*
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* Read the BFAR register via _ScbBusFaultAddrGet() if this routine returns 1,
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* as it will contain the faulting address.
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*
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* @return 1 if so, 0 otherwise
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*/
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static inline int _ScbBusFaultIsPrecise(void)
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{
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return !!__scs.scb.cfsr.byte.bfsr.bit.preciserr;
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}
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/**
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*
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* @brief Find out if a bus fault is an instruction bus error
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*
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* This routine determines if a bus fault is an instruction bus error.
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* It is signalled only if the instruction is issued.
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*
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* @return 1 if so, 0 otherwise
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*/
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static inline int _ScbBusFaultIsInstrBusErr(void)
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{
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return !!__scs.scb.cfsr.byte.bfsr.bit.ibuserr;
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}
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/**
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*
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* @brief Get the faulting address on a precise bus fault
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@ -349,108 +144,6 @@ static inline uint32_t _ScbBusFaultAddrGet(void)
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return __scs.scb.bfar;
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}
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/**
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*
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* @brief Find out if a hard fault is a usage fault
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*
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* This routine determines if a hard fault is a usage fault.
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*
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* @return 1 if so, 0 otherwise
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*/
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static inline int _ScbIsUsageFault(void)
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{
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return !!__scs.scb.cfsr.byte.ufsr.val;
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}
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/**
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*
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* @brief Find out if a usage fault is a 'divide by zero' fault
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*
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* This routine determines if a usage fault is a 'divide by zero' fault.
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*
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* @return 1 if so, 0 otherwise
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*/
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static inline int _ScbUsageFaultIsDivByZero(void)
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{
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return !!__scs.scb.cfsr.byte.ufsr.bit.divbyzero;
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}
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/**
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*
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* @brief Find out if a usage fault is a unaligned access error
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*
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* This routine determines if a usage fault is an unaligned access error.
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*
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* @return 1 if so, 0 otherwise
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*/
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static inline int _ScbUsageFaultIsUnaligned(void)
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{
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return !!__scs.scb.cfsr.byte.ufsr.bit.unaligned;
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}
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/**
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*
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* @brief Find out if a usage fault is a co-processor access error
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*
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* This routine determines if a usage fault is caused by a co-processor access.
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* This happens if the co-processor is either absent or disabled.
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*
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* @return 1 if so, 0 otherwise
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*/
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static inline int _ScbUsageFaultIsNoCp(void)
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{
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return !!__scs.scb.cfsr.byte.ufsr.bit.nocp;
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}
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/**
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*
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* @brief Find out if a usage fault is a invalid PC load error
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*
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* Happens if the the instruction address on an exception return is not
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* halfword-aligned.
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*
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* @return 1 if so, 0 otherwise
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*/
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static inline int _ScbUsageFaultIsInvalidPcLoad(void)
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{
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return !!__scs.scb.cfsr.byte.ufsr.bit.invpc;
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}
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/**
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*
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* @brief Find out if a usage fault is a invalid state error
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*
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* Happens if the the instruction address loaded in the PC via a branch, LDR or
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* POP, or if the instruction address installed in a exception vector, does not
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* have bit 0 set; i.e, is not halfword-aligned.
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*
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* @return 1 if so, 0 otherwise
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*/
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static inline int _ScbUsageFaultIsInvalidState(void)
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{
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return !!__scs.scb.cfsr.byte.ufsr.bit.invstate;
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}
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/**
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*
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* @brief Find out if a usage fault is a undefined instruction error
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*
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* The processor tried to execute an invalid opcode.
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*
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* @return 1 if so, 0 otherwise
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*/
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static inline int _ScbUsageFaultIsUndefinedInstr(void)
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{
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return !!__scs.scb.cfsr.byte.ufsr.bit.undefinstr;
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}
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/**
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*
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* @brief Clear all usage faults (UFSR register)
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