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dts: bindings: clock: Change clock control binding for Renesas RA

Browse source 
Background of this modification is to make clock control
driver code provided by Renesas vendor to support for Renesas MCU
on Zephyr.

Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
This commit is contained in:
Quy Tran 2024-06-20 09:49:31 +00:00 • committed by Anas Nashif
commit d1d42ec7f3
24 changed files with 20 additions and 12 deletions
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2
boards/renesas/ek_ra4e2/doc/index.rst
View file

@ -96,6 +96,8 @@ The below features are currently supported on Zephyr OS for EK-RA4E2 board:
+-----------+------------+----------------------+ +-----------+------------+----------------------+
| UART | on-chip | serial | | UART | on-chip | serial |
+-----------+------------+----------------------+ +-----------+------------+----------------------+
| CLOCK | on-chip | clock control |
+-----------+------------+----------------------+
Other hardware features are currently not supported by the port. Other hardware features are currently not supported by the port.

1
boards/renesas/ek_ra4e2/ek_ra4e2.dts
View file

@ -56,7 +56,6 @@
source = <RA_PLL_SOURCE_MAIN_OSC>; source = <RA_PLL_SOURCE_MAIN_OSC>;
div = <RA_PLL_DIV_1>; div = <RA_PLL_DIV_1>;
mul = <10 0>; mul = <10 0>;
freq = <DT_FREQ_M(200)>;
status = "okay"; status = "okay";
}; };

1
boards/renesas/ek_ra4e2/ek_ra4e2_defconfig
View file

@ -15,3 +15,4 @@ CONFIG_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_BUILD_NO_GAP_FILL=y CONFIG_BUILD_NO_GAP_FILL=y
CONFIG_CLOCK_CONTROL=y

2
boards/renesas/ek_ra4m2/doc/index.rst
View file

@ -96,6 +96,8 @@ The below features are currently supported on Zephyr OS for EK-RA4M2 board:
+-----------+------------+----------------------+ +-----------+------------+----------------------+
| UART | on-chip | serial | | UART | on-chip | serial |
+-----------+------------+----------------------+ +-----------+------------+----------------------+
| CLOCK | on-chip | clock control |
+-----------+------------+----------------------+
Other hardware features are currently not supported by the port. Other hardware features are currently not supported by the port.

1
boards/renesas/ek_ra4m2/ek_ra4m2.dts
View file

@ -56,7 +56,6 @@
source = <RA_PLL_SOURCE_MAIN_OSC>; source = <RA_PLL_SOURCE_MAIN_OSC>;
div = <RA_PLL_DIV_3>; div = <RA_PLL_DIV_3>;
mul = <25 0>; mul = <25 0>;
freq = <DT_FREQ_M(200)>;
status = "okay"; status = "okay";
}; };

1
boards/renesas/ek_ra4m2/ek_ra4m2_defconfig
View file

@ -15,3 +15,4 @@ CONFIG_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_BUILD_NO_GAP_FILL=y CONFIG_BUILD_NO_GAP_FILL=y
CONFIG_CLOCK_CONTROL=y

2
boards/renesas/ek_ra4m3/doc/index.rst
View file

@ -98,6 +98,8 @@ The below features are currently supported on Zephyr OS for EK-RA4M3 board:
+-----------+------------+----------------------+ +-----------+------------+----------------------+
| UART | on-chip | serial | | UART | on-chip | serial |
+-----------+------------+----------------------+ +-----------+------------+----------------------+
| CLOCK | on-chip | clock control |
+-----------+------------+----------------------+
Other hardware features are currently not supported by the port. Other hardware features are currently not supported by the port.

1
boards/renesas/ek_ra4m3/ek_ra4m3.dts
View file

@ -56,7 +56,6 @@
source = <RA_PLL_SOURCE_MAIN_OSC>; source = <RA_PLL_SOURCE_MAIN_OSC>;
div = <RA_PLL_DIV_3>; div = <RA_PLL_DIV_3>;
mul = <25 0>; mul = <25 0>;
freq = <DT_FREQ_M(200)>;
status = "okay"; status = "okay";
}; };

1
boards/renesas/ek_ra4m3/ek_ra4m3_defconfig
View file

@ -15,3 +15,4 @@ CONFIG_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_BUILD_NO_GAP_FILL=y CONFIG_BUILD_NO_GAP_FILL=y
CONFIG_CLOCK_CONTROL=y

2
boards/renesas/ek_ra4w1/doc/index.rst
View file

@ -88,6 +88,8 @@ The below features are currently supported on Zephyr OS for EK-RA4W1 board:
+-----------+------------+----------------------+ +-----------+------------+----------------------+
| UART | on-chip | serial | | UART | on-chip | serial |
+-----------+------------+----------------------+ +-----------+------------+----------------------+
| CLOCK | on-chip | clock control |
+-----------+------------+----------------------+
Other hardware features are currently not supported by the port. Other hardware features are currently not supported by the port.

1
boards/renesas/ek_ra4w1/ek_ra4w1_defconfig
View file

@ -15,3 +15,4 @@ CONFIG_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_BUILD_NO_GAP_FILL=y CONFIG_BUILD_NO_GAP_FILL=y
CONFIG_CLOCK_CONTROL=y

1
dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi
View file

@ -83,7 +83,6 @@
source = <RA_PLL_SOURCE_MAIN_OSC>; source = <RA_PLL_SOURCE_MAIN_OSC>;
div = <RA_PLL_DIV_1>; div = <RA_PLL_DIV_1>;
mul = <10 0>; mul = <10 0>;
freq = <DT_FREQ_M(200)>;
status = "disabled"; status = "disabled";
}; };

1
dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi
View file

@ -133,7 +133,6 @@
div = <RA_PLL_DIV_3>; div = <RA_PLL_DIV_3>;
mul = <25 0>; mul = <25 0>;
status = "disabled"; status = "disabled";
freq = <DT_FREQ_M(200)>;
}; };
pll2: pll2 { pll2: pll2 {

1
dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi
View file

@ -143,7 +143,6 @@
div = <RA_PLL_DIV_3>; div = <RA_PLL_DIV_3>;
mul = <25 0>; mul = <25 0>;
status = "disabled"; status = "disabled";
freq = <DT_FREQ_M(200)>;
}; };
pll2: pll2 { pll2: pll2 {

1
dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi
View file

@ -77,7 +77,6 @@
source = <RA_PLL_SOURCE_MAIN_OSC>; source = <RA_PLL_SOURCE_MAIN_OSC>;
div = <RA_PLL_DIV_2>; div = <RA_PLL_DIV_2>;
mul = <12 0>; mul = <12 0>;
freq = <DT_FREQ_M(48)>;
status = "disabled"; status = "disabled";
}; };

1
soc/renesas/ra/ra4e2/Kconfig
View file

@ -6,6 +6,7 @@ config SOC_SERIES_RA4E2
select CPU_HAS_ARM_MPU select CPU_HAS_ARM_MPU
select CPU_CORTEX_M33 select CPU_CORTEX_M33
select HAS_RENESAS_RA_FSP select HAS_RENESAS_RA_FSP
select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
select CPU_CORTEX_M_HAS_DWT select CPU_CORTEX_M_HAS_DWT
select ARMV8_M_DSP select ARMV8_M_DSP
select CPU_HAS_FPU select CPU_HAS_FPU

2
soc/renesas/ra/ra4e2/soc.c
View file

@ -37,6 +37,7 @@ volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
static int renesas_ra4e2_init(void) static int renesas_ra4e2_init(void)
{ {
extern volatile uint16_t g_protect_counters[]; extern volatile uint16_t g_protect_counters[];
for (uint32_t i = 0; i < 4; i++) { for (uint32_t i = 0; i < 4; i++) {
g_protect_counters[i] = 0; g_protect_counters[i] = 0;
} }
@ -61,7 +62,6 @@ static int renesas_ra4e2_init(void)
SystemCoreClock = BSP_MOCO_HZ; SystemCoreClock = BSP_MOCO_HZ;
g_protect_pfswe_counter = 0; g_protect_pfswe_counter = 0;
bsp_clock_init();
return 0; return 0;
} }

2
soc/renesas/ra/ra4e2/soc.h
View file

@ -13,4 +13,4 @@
#include <bsp_api.h> #include <bsp_api.h>
#endif /* ZEPHYR_SOC_RENESAS_RA4_SOC_H_ */ #endif /* ZEPHYR_SOC_RENESAS_RA4E2_SOC_H_ */

1
soc/renesas/ra/ra4m2/Kconfig
View file

@ -7,6 +7,7 @@ config SOC_SERIES_RA4M2
select CPU_CORTEX_M33 select CPU_CORTEX_M33
select HAS_RENESAS_RA_FSP select HAS_RENESAS_RA_FSP
select CPU_CORTEX_M_HAS_DWT select CPU_CORTEX_M_HAS_DWT
select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
select ARMV8_M_DSP select ARMV8_M_DSP
select CPU_HAS_FPU select CPU_HAS_FPU
select FPU select FPU

2
soc/renesas/ra/ra4m2/soc.c
View file

@ -37,6 +37,7 @@ volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
static int renesas_ra4m2_init(void) static int renesas_ra4m2_init(void)
{ {
extern volatile uint16_t g_protect_counters[]; extern volatile uint16_t g_protect_counters[];
for (uint32_t i = 0; i < 4; i++) { for (uint32_t i = 0; i < 4; i++) {
g_protect_counters[i] = 0; g_protect_counters[i] = 0;
} }
@ -61,7 +62,6 @@ static int renesas_ra4m2_init(void)
SystemCoreClock = BSP_MOCO_HZ; SystemCoreClock = BSP_MOCO_HZ;
g_protect_pfswe_counter = 0; g_protect_pfswe_counter = 0;
bsp_clock_init();
return 0; return 0;
} }

1
soc/renesas/ra/ra4m3/Kconfig
View file

@ -6,6 +6,7 @@ config SOC_SERIES_RA4M3
select CPU_HAS_ARM_MPU select CPU_HAS_ARM_MPU
select CPU_CORTEX_M33 select CPU_CORTEX_M33
select HAS_RENESAS_RA_FSP select HAS_RENESAS_RA_FSP
select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
select CPU_CORTEX_M_HAS_DWT select CPU_CORTEX_M_HAS_DWT
select ARMV8_M_DSP select ARMV8_M_DSP
select CPU_HAS_FPU select CPU_HAS_FPU

2
soc/renesas/ra/ra4m3/soc.c
View file

@ -37,6 +37,7 @@ volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
static int renesas_ra4m3_init(void) static int renesas_ra4m3_init(void)
{ {
extern volatile uint16_t g_protect_counters[]; extern volatile uint16_t g_protect_counters[];
for (uint32_t i = 0; i < 4; i++) { for (uint32_t i = 0; i < 4; i++) {
g_protect_counters[i] = 0; g_protect_counters[i] = 0;
} }
@ -61,7 +62,6 @@ static int renesas_ra4m3_init(void)
SystemCoreClock = BSP_MOCO_HZ; SystemCoreClock = BSP_MOCO_HZ;
g_protect_pfswe_counter = 0; g_protect_pfswe_counter = 0;
bsp_clock_init();
return 0; return 0;
} }

1
soc/renesas/ra/ra4w1/Kconfig
View file

@ -6,6 +6,7 @@ config SOC_SERIES_RA4W1
select CPU_HAS_ARM_MPU select CPU_HAS_ARM_MPU
select CPU_CORTEX_M4 select CPU_CORTEX_M4
select HAS_RENESAS_RA_FSP select HAS_RENESAS_RA_FSP
select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
select CPU_CORTEX_M_HAS_DWT select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU select CPU_HAS_FPU
select FPU select FPU

1
soc/renesas/ra/ra4w1/soc.c
View file

@ -38,7 +38,6 @@ static int renesas_ra4w1_init(void)
{ {
SystemCoreClock = BSP_MOCO_HZ; SystemCoreClock = BSP_MOCO_HZ;
g_protect_pfswe_counter = 0; g_protect_pfswe_counter = 0;
bsp_clock_init();
return 0; return 0;
} }