dts: bindings: clock: Change clock control binding for Renesas RA

Background of this modification is to make clock control
driver code provided by Renesas vendor to support for Renesas MCU
on Zephyr.

Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>

soc/renesas/ra/ra4e2/Kconfig

@@ -6,6 +6,7 @@ config SOC_SERIES_RA4E2
 	select CPU_HAS_ARM_MPU
 	select CPU_CORTEX_M33
 	select HAS_RENESAS_RA_FSP
+	select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
 	select CPU_CORTEX_M_HAS_DWT
 	select ARMV8_M_DSP
 	select CPU_HAS_FPU

soc/renesas/ra/ra4e2/soc.c

@@ -37,6 +37,7 @@ volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
 static int renesas_ra4e2_init(void)
 {
 	extern volatile uint16_t g_protect_counters[];
+
 	for (uint32_t i = 0; i < 4; i++) {
 		g_protect_counters[i] = 0;
 	}
@@ -61,7 +62,6 @@ static int renesas_ra4e2_init(void)
 
 	SystemCoreClock = BSP_MOCO_HZ;
 	g_protect_pfswe_counter = 0;
-	bsp_clock_init();
 
 	return 0;
 }

soc/renesas/ra/ra4e2/soc.h

@@ -13,4 +13,4 @@
 
 #include <bsp_api.h>
 
-#endif /* ZEPHYR_SOC_RENESAS_RA4_SOC_H_ */
+#endif /* ZEPHYR_SOC_RENESAS_RA4E2_SOC_H_ */

soc/renesas/ra/ra4m2/Kconfig

@@ -7,6 +7,7 @@ config SOC_SERIES_RA4M2
 	select CPU_CORTEX_M33
 	select HAS_RENESAS_RA_FSP
 	select CPU_CORTEX_M_HAS_DWT
+	select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
 	select ARMV8_M_DSP
 	select CPU_HAS_FPU
 	select FPU

soc/renesas/ra/ra4m2/soc.c

@@ -37,6 +37,7 @@ volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
 static int renesas_ra4m2_init(void)
 {
 	extern volatile uint16_t g_protect_counters[];
+
 	for (uint32_t i = 0; i < 4; i++) {
 		g_protect_counters[i] = 0;
 	}
@@ -61,7 +62,6 @@ static int renesas_ra4m2_init(void)
 
 	SystemCoreClock = BSP_MOCO_HZ;
 	g_protect_pfswe_counter = 0;
-	bsp_clock_init();
 
 	return 0;
 }

soc/renesas/ra/ra4m3/Kconfig

@@ -6,6 +6,7 @@ config SOC_SERIES_RA4M3
 	select CPU_HAS_ARM_MPU
 	select CPU_CORTEX_M33
 	select HAS_RENESAS_RA_FSP
+	select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
 	select CPU_CORTEX_M_HAS_DWT
 	select ARMV8_M_DSP
 	select CPU_HAS_FPU

soc/renesas/ra/ra4m3/soc.c

@@ -37,6 +37,7 @@ volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
 static int renesas_ra4m3_init(void)
 {
 	extern volatile uint16_t g_protect_counters[];
+
 	for (uint32_t i = 0; i < 4; i++) {
 		g_protect_counters[i] = 0;
 	}
@@ -61,7 +62,6 @@ static int renesas_ra4m3_init(void)
 
 	SystemCoreClock = BSP_MOCO_HZ;
 	g_protect_pfswe_counter = 0;
-	bsp_clock_init();
 
 	return 0;
 }

soc/renesas/ra/ra4w1/Kconfig

@@ -6,6 +6,7 @@ config SOC_SERIES_RA4W1
 	select CPU_HAS_ARM_MPU
 	select CPU_CORTEX_M4
 	select HAS_RENESAS_RA_FSP
+	select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
 	select CPU_CORTEX_M_HAS_DWT
 	select CPU_HAS_FPU
 	select FPU

soc/renesas/ra/ra4w1/soc.c

@@ -38,7 +38,6 @@ static int renesas_ra4w1_init(void)
 {
 	SystemCoreClock = BSP_MOCO_HZ;
 	g_protect_pfswe_counter = 0;
-	bsp_clock_init();
 
 	return 0;
 }