riscv32: added the riscv-privilege SOC_FAMILY

added the riscv-privilege SOC_FAMILY, under which all
riscv SOCs supporting the riscv privilege architecture
specifcation shall reside. These SOCs shall notably have
a common base for handling IRQs.

Moved riscv32-qemu under the riscv-privilege SOC_FAMILY

Change-Id: I5372cb38e3eaed78886f22b212ab4f881ef30b3f
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>

arch/riscv32/Kbuild

@@ -2,5 +2,10 @@ subdir-ccflags-y +=-I$(srctree)/include/drivers
 subdir-ccflags-y +=-I$(srctree)/drivers
 subdir-asflags-y += $(subdir-ccflags-y)
 
+ifneq ($(SOC_FAMILY),)
+obj-y += soc/$(SOC_FAMILY)/
+else
 obj-y += soc/$(SOC_PATH)/
+endif
+
 obj-y += core/

arch/riscv32/Makefile

@@ -14,7 +14,3 @@ soc-aflags ?= $(soc-cflags)
 KBUILD_CFLAGS += $(soc-cflags)
 KBUILD_CXXFLAGS += $(soc-cxxflags)
 KBUILD_AFLAGS += $(soc-aflags)
-
-soc_ld_include := -I$(srctree)/arch/$(ARCH)/soc \
-		  -I$(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/
-EXTRA_LINKER_CMD_OPT += $(soc_ld_include)

arch/riscv32/soc/riscv-privilege/Kconfig

@@ -0,0 +1,9 @@
+# Kconfig - configuration options for riscv SOCs supporting
+#           the riscv privileged architecture specification
+#
+# Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+source "arch/riscv32/soc/riscv-privilege/*/Kconfig.soc"

arch/riscv32/soc/riscv-privilege/Kconfig.defconfig

@@ -0,0 +1,18 @@
+# Kconfig - riscv SOC family supporting the riscv privileged architecture spec
+#
+# Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SOC_FAMILY_RISCV_PRIVILEGE
+	bool
+	# omit prompt to signify a "hidden" option
+	default n
+
+config SOC_FAMILY
+	string
+	default "riscv-privilege"
+	depends on SOC_FAMILY_RISCV_PRIVILEGE
+
+source "arch/riscv32/soc/riscv-privilege/*/Kconfig.defconfig.series"

arch/riscv32/soc/riscv-privilege/Kconfig.soc

@@ -0,0 +1,8 @@
+# Kconfig - riscv SOC series supporting the riscv privileged architecture spec
+#
+# Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+source "arch/riscv32/soc/riscv-privilege/*/Kconfig.series"

arch/riscv32/soc/riscv-privilege/Makefile

@@ -0,0 +1,9 @@
+# Kconfig - riscv SOC family supporting the riscv privileged architecture spec
+#
+# Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+obj-y += $(SOC_SERIES)/
+obj-y += common/

arch/riscv32/soc/riscv-privilege/common/Makefile

@@ -0,0 +1,8 @@
+# Kconfig - SOC_FAMILY_RISCV_PRIVILEGE common functionalities
+#
+# Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+obj-y += soc_common_irq.o soc_irq.o

arch/riscv32/soc/riscv-privilege/common/soc_common.h

@@ -9,8 +9,8 @@
  *       privileged architecture specification
  */
 
-#ifndef __RISCV_PRIVILEGE_H_
-#define __RISCV_PRIVILEGE_H_
+#ifndef __SOC_COMMON_H_
+#define __SOC_COMMON_H_
 
 /* IRQ numbers */
 #define RISCV_MACHINE_SOFT_IRQ       3  /* Machine Software Interrupt */
@@ -51,4 +51,12 @@
 /* SOC-Specific EXIT ISR command */
 #define SOC_ERET                     mret
 
-#endif /* __RISCV_PRIVILEGE_H_ */
+#ifndef _ASMLANGUAGE
+
+#if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT)
+void soc_interrupt_init(void);
+#endif
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* __SOC_COMMON_H_ */

arch/riscv32/soc/riscv-privilege/common/soc_common_irq.c

@@ -1,23 +1,22 @@
 /*
- * Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
+ * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
  * @file
- * @brief riscv32-qemu interrupt management code
+ * @brief interrupt management code for riscv SOCs supporting the riscv
+	  privileged architecture specification
  */
 #include <irq.h>
-#include <soc.h>
 
+/* TODO: account for RISCV PLIC */
 void _arch_irq_enable(unsigned int irq)
 {
 	uint32_t mie;
 
 	/*
-	 * Since only internal Timer device has interrupt within in
-	 * riscv32-qemu, use only mie CSR register to enable device interrupt.
 	 * CSR mie register is updated using atomic instruction csrrs
 	 * (atomic read and set bits in CSR register)
 	 */
@@ -55,8 +54,6 @@ void soc_interrupt_init(void)
 	(void)irq_lock();
 
 	__asm__ volatile ("csrwi mie, 0\n"
-			  "csrwi sie, 0\n"
-			  "csrwi mip, 0\n"
-			  "csrwi sip, 0\n");
+			  "csrwi mip, 0\n");
 }
 #endif

arch/riscv32/soc/riscv-privilege/common/soc_irq.S

@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * common interrupt management code for riscv SOCs supporting the riscv
+ * privileged architecture specification
+ */
+#include <kernel_structs.h>
+#include <offsets.h>
+#include <toolchain.h>
+#include <sections.h>
+#include <soc.h>
+
+/* exports */
+GTEXT(__soc_handle_irq)
+
+/*
+ * SOC-specific function to handle pending IRQ number generating the interrupt.
+ * Exception number is given as parameter via register a0.
+ */
+SECTION_FUNC(exception.other, __soc_handle_irq)
+	/* Clear exception number from CSR mip register */
+	li t1, 1
+	sll t0, t1, a0
+	csrrc t1, mip, t0
+
+	/* Return */
+	jalr x0, ra
+
+/*
+ * __soc_is_irq is defined as .weak to allow re-implementation by
+ * SOCs that does not truely follow the riscv privilege specification.
+ */
+WTEXT(__soc_is_irq)
+
+/*
+ * SOC-specific function to determine if the exception is the result of a
+ * an interrupt or an exception
+ * return 1 (interrupt) or 0 (exception)
+ *
+ */
+SECTION_FUNC(exception.other, __soc_is_irq)
+	/* Read mcause and check if interrupt bit is set */
+	csrr t0, mcause
+	li t1, SOC_MCAUSE_IRQ_MASK
+	and t0, t0, t1
+
+	/* If interrupt bit is not set, return with 0 */
+	addi a0, x0, 0
+	beqz t0, not_interrupt
+	addi a0, a0, 1
+
+not_interrupt:
+	/* return */
+	jalr x0, ra

arch/riscv32/soc/riscv-privilege/riscv32-qemu/Kconfig.defconfig.series

@@ -1,6 +1,6 @@
-if SOC_RISCV32_QEMU
+if SOC_SERIES_RISCV32_QEMU
 
-config SOC
+config SOC_SERIES
 	string
 	default "riscv32-qemu"
 
@@ -36,4 +36,4 @@ config RISCV_RAM_SIZE_MB
 	int
 	default 32
 
-endif # SOC_RISCV32_QEMU
+endif # SOC_SERIES_RISCV32_QEMU

arch/riscv32/soc/riscv-privilege/riscv32-qemu/Kconfig.series

@@ -0,0 +1,13 @@
+# Kconfig - riscv32 QEMU SOC implementation
+#
+# Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SOC_SERIES_RISCV32_QEMU
+	bool "riscv32 QEMU SOC implementation"
+	depends on RISCV32
+	select SOC_FAMILY_RISCV_PRIVILEGE
+	help
+	Enable support for riscv32 QEMU SOC implementation

arch/riscv32/soc/riscv-privilege/riscv32-qemu/Kconfig.soc

@@ -0,0 +1,16 @@
+# Kconfig - RISCV32_QEMU SOC configuration options
+#
+# Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+choice
+prompt "riscv32_qemu SOC implementation"
+depends on SOC_SERIES_RISCV32_QEMU
+
+config SOC_RISCV32_QEMU
+	bool "riscv32_qemu SOC implementation"
+	select ATOMIC_OPERATIONS_C
+
+endchoice

arch/riscv32/soc/riscv-privilege/riscv32-qemu/Makefile

@@ -0,0 +1,7 @@
+soc-cflags := -I/$(srctree)/arch/$(ARCH)/soc/$(SOC_FAMILY)/common/
+
+obj-y += qemu_irq.o vector.o
+
+soc_ld_include := -I$(srctree)/arch/$(ARCH)/soc/$(SOC_FAMILY)/common/ \
+		  -I$(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/
+EXTRA_LINKER_CMD_OPT += $(soc_ld_include)

arch/riscv32/soc/riscv-privilege/riscv32-qemu/qemu_irq.S

@@ -12,25 +12,12 @@
 
 /* exports */
 GTEXT(__soc_is_irq)
-GTEXT(__soc_handle_irq)
 
 /*
- * SOC-specific function to handle pending IRQ number generating the interrupt.
- * Exception number is given as parameter via register a0.
- */
-SECTION_FUNC(exception.other, __soc_handle_irq)
-	/* Clear exception number from CSR mip register */
-	li t1, 1
-	sll t0, t1, a0
-	csrrc t1, mip, t0
-
-	/* Return */
-	jalr x0, ra
-
-
-/*
- * SOC-specific function to determine if the exception is the result of a
- * an interrupt or an exception
+ * riscv32-qemu does not truely follow riscv privilege specification
+ * when determining if exception is the result of an interrupt or an
+ * exception. Hence, reimplement __soc_is_irq here.
+ *
  * return 1 (interrupt) or 0 (exception)
  */
 SECTION_FUNC(exception.other, __soc_is_irq)

arch/riscv32/soc/riscv-privilege/riscv32-qemu/soc.h

@@ -11,7 +11,7 @@
 #ifndef __RISCV32_QEMU_SOC_H_
 #define __RISCV32_QEMU_SOC_H_
 
-#include <riscv-privilege.h>
+#include <soc_common.h>
 
 #include <misc/util.h>
 
@@ -23,16 +23,7 @@
 #define RISCV_MTIMECMP_BASE          0x40000008
 
 /* lib-c hooks required RAM defined variables */
-#define RISCV_RAM_BASE             CONFIG_RISCV_RAM_BASE_ADDR
-#define RISCV_RAM_SIZE             MB(CONFIG_RISCV_RAM_SIZE_MB)
-
-#ifndef _ASMLANGUAGE
-#include <irq.h>
-
-#if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT)
-void soc_interrupt_init(void);
-#endif
-
-#endif /* !_ASMLANGUAGE */
+#define RISCV_RAM_BASE               CONFIG_RISCV_RAM_BASE_ADDR
+#define RISCV_RAM_SIZE               MB(CONFIG_RISCV_RAM_SIZE_MB)
 
 #endif /* __RISCV32_QEMU_SOC_H_ */

arch/riscv32/soc/riscv32-qemu/Kbuild

@@ -1,7 +0,0 @@
-ccflags-y +=-I$(srctree)/include
-ccflags-y +=-I$(srctree)/include/drivers
-ccflags-y +=-I$(srctree)/drivers
-
-asflags-y := ${ccflags-y}
-
-obj-y = soc_irq.o vector.o qemu_irq.o

arch/riscv32/soc/riscv32-qemu/Kconfig.soc

@@ -1,3 +0,0 @@
-config SOC_RISCV32_QEMU
-	bool "riscv32_qemu SOC implementation"
-	select ATOMIC_OPERATIONS_C

arch/riscv32/soc/riscv32-qemu/Makefile

@@ -1,2 +0,0 @@
-soc-cflags := -I/$(srctree)/arch/$(ARCH)/soc/ \
-	      -I/$(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/

boards/riscv32/qemu_riscv32/qemu_riscv32_defconfig

@@ -1,4 +1,5 @@
 CONFIG_RISCV32=y
+CONFIG_SOC_SERIES_RISCV32_QEMU=y
 CONFIG_SOC_RISCV32_QEMU=y
 CONFIG_BOARD_QEMU_RISCV32=y
 CONFIG_CONSOLE=y