diff --git a/arch/arm/core/cortex_a_r/swap.c b/arch/arm/core/cortex_a_r/swap.c
index 258999be7c7..2f7faba741a 100644
--- a/arch/arm/core/cortex_a_r/swap.c
+++ b/arch/arm/core/cortex_a_r/swap.c
@@ -7,7 +7,7 @@
 #include <zephyr/kernel.h>
 #include <kernel_internal.h>
 
-extern const int _k_neg_eagain;
+#include <errno.h>
 
 /* The 'key' actually represents the BASEPRI register
  * prior to disabling interrupts via the BASEPRI mechanism.
@@ -18,7 +18,7 @@ int arch_swap(unsigned int key)
 {
 	/* store off key and return value */
 	_current->arch.basepri = key;
-	_current->arch.swap_return_value = _k_neg_eagain;
+	_current->arch.swap_return_value = -EAGAIN;
 
 	z_arm_cortex_r_svc();
 	irq_unlock(key);
diff --git a/arch/arm/core/cortex_m/swap.c b/arch/arm/core/cortex_m/swap.c
index f41ae2e4e84..9a597ef219d 100644
--- a/arch/arm/core/cortex_m/swap.c
+++ b/arch/arm/core/cortex_m/swap.c
@@ -7,7 +7,7 @@
 #include <zephyr/kernel.h>
 #include <kernel_internal.h>
 
-extern const int _k_neg_eagain;
+#include <errno.h>
 
 /* The 'key' actually represents the BASEPRI register
  * prior to disabling interrupts via the BASEPRI mechanism.
@@ -34,7 +34,7 @@ int arch_swap(unsigned int key)
 {
 	/* store off key and return value */
 	_current->arch.basepri = key;
-	_current->arch.swap_return_value = _k_neg_eagain;
+	_current->arch.swap_return_value = -EAGAIN;
 
 	/* set pending bit to make sure we will take a PendSV exception */
 	SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;