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arch/xtensa: Use ZSR assignments for interrupt return

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We had a similar sequence for interrupt return, where we were
selecting (actually only for the benefit of qemu) the highest priority
EPCn/EPSn registers for our RFI instruction.  That works much better
in python the preprocessor.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit is contained in:
Andy Ross 2022-01-08 16:16:30 -08:00 • committed by Anas Nashif
commit d175c18cbb
1 changed files with 5 additions and 39 deletions
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44
arch/xtensa/core/xtensa-asm2-util.S
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@ -141,51 +141,17 @@ _high_restore_done:
* RFI levels do the same thing and differ only in the special * RFI levels do the same thing and differ only in the special
* registers used to hold PC/PS, but Qemu has been observed to behave * registers used to hold PC/PS, but Qemu has been observed to behave
* strangely when RFI doesn't "return" to a INTLEVEL strictly lower * strangely when RFI doesn't "return" to a INTLEVEL strictly lower
* than it started from. So pick level 6 (the highest that works on * than it started from. So we leverage the zsr.h framework to pick
* Qemu, hardware doesn't care so it doesn't matter). In theory we * the highest level available for our specific platform.
* should test to be able to support hardware with less than 6 levels,
* though...
*/ */
/*
* XCC doesn't like _CONCAT() so we need to spell out
* every single one.
*/
#if XCHAL_NUM_INTLEVELS == 1
# define RCTX_EPC_REG EPC1
# define RCTX_EPS_REG EPS1
#elif XCHAL_NUM_INTLEVELS == 2
# define RCTX_EPC_REG EPC2
# define RCTX_EPS_REG EPS2
#elif XCHAL_NUM_INTLEVELS == 3
# define RCTX_EPC_REG EPC3
# define RCTX_EPS_REG EPS3
#elif XCHAL_NUM_INTLEVELS == 4
# define RCTX_EPC_REG EPC4
# define RCTX_EPS_REG EPS4
#elif XCHAL_NUM_INTLEVELS == 5
# define RCTX_EPC_REG EPC5
# define RCTX_EPS_REG EPS5
#elif XCHAL_NUM_INTLEVELS == 6
# define RCTX_EPC_REG EPC6
# define RCTX_EPS_REG EPS6
#elif XCHAL_NUM_INTLEVELS == 7
# define RCTX_EPC_REG EPC7
# define RCTX_EPS_REG EPS7
#else
/* Catch all */
# define RCTX_EPC_REG _CONCAT(EPC, XCHAL_NUM_INTLEVELS)
# define RCTX_EPS_REG _CONCAT(EPS, XCHAL_NUM_INTLEVELS)
#endif
.global _restore_context .global _restore_context
_restore_context: _restore_context:
call0 xtensa_restore_high_regs call0 xtensa_restore_high_regs
l32i a0, a1, BSA_PC_OFF l32i a0, a1, BSA_PC_OFF
wsr a0, RCTX_EPC_REG wsr a0, ZSR_EPC
l32i a0, a1, BSA_PS_OFF l32i a0, a1, BSA_PS_OFF
wsr a0, RCTX_EPS_REG wsr a0, ZSR_EPS
l32i a0, a1, BSA_SAR_OFF l32i a0, a1, BSA_SAR_OFF
wsr a0, SAR wsr a0, SAR
@ -212,7 +178,7 @@ _restore_context:
l32i a3, a1, BSA_A3_OFF l32i a3, a1, BSA_A3_OFF
addi a1, a1, BASE_SAVE_AREA_SIZE addi a1, a1, BASE_SAVE_AREA_SIZE
rfi XCHAL_NUM_INTLEVELS rfi ZSR_RFI_LEVEL
/* /*
* void xtensa_switch(void *new, void **old_return); * void xtensa_switch(void *new, void **old_return);