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ITE drivers/kscan: add keyboard scan driver for it8xxx2_evb

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Add keyboard scan driver for board it8xxx2_evb.

Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
This commit is contained in:
Ruibin Chang 2020-11-10 14:49:52 +08:00 • committed by Christopher Friedt
commit d16ae76d30
12 changed files with 729 additions and 106 deletions
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152
soc/riscv/riscv-ite/common/chip_chipregs.h
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@ -1,4 +1,4 @@
/*
/*
* Copyright (c) 2020 ITE Corporation. All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*/
@ -995,114 +995,54 @@ struct pwm_it8xxx2_regs {
/**
*
* (1Dxxh) Keyboard Matrix Scan control (KBS)
* (1Dxxh) Keyboard Matrix Scan control (KSCAN)
*
*/
#define KSOL ECREG(EC_REG_BASE_ADDR + 0x1D00)
#define KSOH1 ECREG(EC_REG_BASE_ADDR + 0x1D01)
#define KSOCTRL ECREG(EC_REG_BASE_ADDR + 0x1D02)
#define KSOH2 ECREG(EC_REG_BASE_ADDR + 0x1D03)
#define KSI ECREG(EC_REG_BASE_ADDR + 0x1D04)
#define KSICTRL ECREG(EC_REG_BASE_ADDR + 0x1D05)
#define KSIGCTRL ECREG(EC_REG_BASE_ADDR + 0x1D06)
#define KSIGOEN ECREG(EC_REG_BASE_ADDR + 0x1D07)
#define KSIGDAT ECREG(EC_REG_BASE_ADDR + 0x1D08)
#define KSIGDMRR ECREG(EC_REG_BASE_ADDR + 0x1D09)
#define KSOHGCTRL ECREG(EC_REG_BASE_ADDR + 0x1D0A)
#define KSOHGOEN ECREG(EC_REG_BASE_ADDR + 0x1D0B)
#define KSOHGDMRR ECREG(EC_REG_BASE_ADDR + 0x1D0C)
#define KSOLGCTRL ECREG(EC_REG_BASE_ADDR + 0x1D0D)
#define KSOLGOEN ECREG(EC_REG_BASE_ADDR + 0x1D0E)
#define KSOLGDMRR ECREG(EC_REG_BASE_ADDR + 0x1D0F)
#define KSO0LSDR ECREG(EC_REG_BASE_ADDR + 0x1D10)
#define KSO1LSDR ECREG(EC_REG_BASE_ADDR + 0x1D11)
#define KSO2LSDR ECREG(EC_REG_BASE_ADDR + 0x1D12)
#define KSO3LSDR ECREG(EC_REG_BASE_ADDR + 0x1D13)
#define KSO4LSDR ECREG(EC_REG_BASE_ADDR + 0x1D14)
#define KSO5LSDR ECREG(EC_REG_BASE_ADDR + 0x1D15)
#define KSO6LSDR ECREG(EC_REG_BASE_ADDR + 0x1D16)
#define KSO7LSDR ECREG(EC_REG_BASE_ADDR + 0x1D17)
#define KSO8LSDR ECREG(EC_REG_BASE_ADDR + 0x1D18)
#define KSO9LSDR ECREG(EC_REG_BASE_ADDR + 0x1D19)
#define KSO10LSDR ECREG(EC_REG_BASE_ADDR + 0x1D1A)
#define KSO11LSDR ECREG(EC_REG_BASE_ADDR + 0x1D1B)
#define KSO12LSDR ECREG(EC_REG_BASE_ADDR + 0x1D1C)
#define KSO13LSDR ECREG(EC_REG_BASE_ADDR + 0x1D1D)
#define KSO14LSDR ECREG(EC_REG_BASE_ADDR + 0x1D1E)
#define KSO15LSDR ECREG(EC_REG_BASE_ADDR + 0x1D1F)
#define KSO16LSDR ECREG(EC_REG_BASE_ADDR + 0x1D20)
#define KSO17LSDR ECREG(EC_REG_BASE_ADDR + 0x1D21)
#define SDC1R ECREG(EC_REG_BASE_ADDR + 0x1D22)
#define SDEN BIT(7)
#define INTSDVEN BIT(5)
#ifndef __ASSEMBLER__
struct kscan_it8xxx2_regs {
/* 0x000: Keyboard Scan Out */
volatile uint8_t KBS_KSOL;
/* 0x001: Keyboard Scan Out */
volatile uint8_t KBS_KSOH1;
/* 0x002: Keyboard Scan Out Control */
volatile uint8_t KBS_KSOCTRL;
/* 0x003: Keyboard Scan Out */
volatile uint8_t KBS_KSOH2;
/* 0x004: Keyboard Scan In */
volatile uint8_t KBS_KSI;
/* 0x005: Keyboard Scan In Control */
volatile uint8_t KBS_KSICTRL;
/* 0x006: Keyboard Scan In [7:0] GPIO Control */
volatile uint8_t KBS_KSIGCTRL;
/* 0x007: Keyboard Scan In [7:0] GPIO Output Enable */
volatile uint8_t KBS_KSIGOEN;
/* 0x008: Keyboard Scan In [7:0] GPIO Data */
volatile uint8_t KBS_KSIGDAT;
/* 0x009: Keyboard Scan In [7:0] GPIO Data Mirror */
volatile uint8_t KBS_KSIGDMRR;
/* 0x00A: Keyboard Scan Out [15:8] GPIO Control */
volatile uint8_t KBS_KSOHGCTRL;
/* 0x00B: Keyboard Scan Out [15:8] GPIO Output Enable */
volatile uint8_t KBS_KSOHGOEN;
/* 0x00C: Keyboard Scan Out [15:8] GPIO Data Mirror */
volatile uint8_t KBS_KSOHGDMRR;
/* 0x00D: Keyboard Scan Out [7:0] GPIO Control */
volatile uint8_t KBS_KSOLGCTRL;
/* 0x00E: Keyboard Scan Out [7:0] GPIO Output Enable */
volatile uint8_t KBS_KSOLGOEN;
};
#endif /* !__ASSEMBLER__ */
/* BIT2 ~ BIT0 Scan loop select */
#define SLS_00_ROUND 0x00
#define SLS_02_ROUND 0x01
#define SLS_03_ROUND 0x02
#define SLS_04_ROUND 0x03
#define SLS_05_ROUND 0x04
#define SLS_06_ROUND 0x05
#define SLS_07_ROUND 0x06
#define SLS_08_ROUND 0x07
#define SDC2R ECREG(EC_REG_BASE_ADDR + 0x1D23)
#define KSOPCS1 BIT(7)
#define KSOPCS0 BIT(6)
/* BIT3 ~ BIT0 Wait KSO high delay */
#define WKSOHDLY_23US 0x00
#define WKSOHDLY_31US 0x01
#define WKSOHDLY_39US 0x02
#define WKSOHDLY_47US 0x03
#define WKSOHDLY_55US 0x04
#define WKSOHDLY_63US 0x05
#define WKSOHDLY_71US 0x06
#define WKSOHDLY_79US 0x07
#define WKSOHDLY_87US 0x08
#define WKSOHDLY_95US 0x09
#define SDC3R ECREG(EC_REG_BASE_ADDR + 0x1D24)
/* BIT7 ~ BIT4 Wait KSO low delay */
#define WKSOLDLY_11US (0x00 << 4)
#define WKSOLDLY_13US (0x01 << 4)
#define WKSOLDLY_15US (0x02 << 4)
#define WKSOLDLY_17US (0x03 << 4)
#define WKSOLDLY_19US (0x04 << 4)
#define WKSOLDLY_21US (0x05 << 4)
#define WKSOLDLY_23US (0x06 << 4)
#define WKSOLDLY_25US (0x07 << 4)
#define WKSOLDLY_27US (0x08 << 4)
#define WKSOLDLY_29US (0x09 << 4)
/* BIT3 ~ BIT0 Spacing delay between rounds */
#define SDLYBR_00MS 0x00
#define SDLYBR_01MS 0x01
#define SDLYBR_02MS 0x02
#define SDLYBR_03MS 0x03
#define SDLYBR_04MS 0x04
#define SDLYBR_05MS 0x05
#define SDLYBR_06MS 0x06
#define SDLYBR_07MS 0x07
#define SDLYBR_08MS 0x08
#define SDLYBR_09MS 0x09
#define SDLYBR_10MS 0x0A
#define SDLYBR_11MS 0x0B
#define SDLYBR_12MS 0x0C
#define SDLYBR_13MS 0x0D
#define SDLYBR_14MS 0x0E
#define SDLYBR_15MS 0x0F
#define SDSR ECREG(EC_REG_BASE_ADDR + 0x1D25)
#define SDV BIT(0)
/* Keyboard Scan Out Control Register */
#define KSOPU BIT(2)
#define KSOOD BIT(0)
/* Keyboard Scan In Control Register */
#define KSIPU BIT(2)
/* KBS register fields */
/* 0x002: Keyboard Scan Out Control */
#define IT8XXX2_KBS_KSOPU BIT(2)
#define IT8XXX2_KBS_KSOOD BIT(0)
/* 0x005: Keyboard Scan In Control */
#define IT8XXX2_KBS_KSIPU BIT(2)
/* 0x00D: Keyboard Scan Out [7:0] GPIO Control */
#define IT8XXX2_KBS_KSO2GCTRL BIT(2)
/* 0x00E: Keyboard Scan Out [7:0] GPIO Output Enable */
#define IT8XXX2_KBS_KSO2GOEN BIT(2)
/**
*