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gcov: Add coverage support for arc nsim platform

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* add toolchain abstraction for coverage
* add select HAS_COVERAGE_SUPPORT to kconfig
* port gcov linker code to CKake for arc
* give user permission to gcov bss section
* expand the size of iccm and dccm to 1M

Signed-off-by: Jingru Wang <jingru@synopsys.com>
This commit is contained in:
Jingru Wang 2020-07-16 15:55:18 +08:00 • committed by Anas Nashif
commit d1665d32f4
6 changed files with 20 additions and 7 deletions
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1
boards/arc/nsim/Kconfig.board
View file

@ -6,6 +6,7 @@
config BOARD_NSIM config BOARD_NSIM
bool "ARC nSIM simulator" bool "ARC nSIM simulator"
depends on SOC_NSIM depends on SOC_NSIM
select HAS_COVERAGE_SUPPORT
help help
The DesignWare ARC nSIM board is a virtual board based on The DesignWare ARC nSIM board is a virtual board based on
the ARC nSIM simulator. It demonstrates the ARC core features the ARC nSIM simulator. It demonstrates the ARC core features

9
boards/arc/nsim/arc_mpu_regions.c
View file

@ -14,6 +14,15 @@
* All regions not listed here are shared by secure world and normal world. * All regions not listed here are shared by secure world and normal world.
*/ */
static struct arc_mpu_region mpu_regions[] = { static struct arc_mpu_region mpu_regions[] = {
#if defined(CONFIG_COVERAGE_GCOV) && defined(CONFIG_USERSPACE)
/* Region Coverage */
MPU_REGION_ENTRY("COVERAGE",
(uint32_t)&(__gcov_bss_start),
(uint32_t)&__gcov_bss_size,
REGION_IO_ATTR),
#endif /* CONFIG_COVERAGE_GCOV && CONFIG_USERSPACE */
#if DT_REG_SIZE(DT_INST(0, arc_iccm)) > 0 #if DT_REG_SIZE(DT_INST(0, arc_iccm)) > 0
/* Region ICCM */ /* Region ICCM */
MPU_REGION_ENTRY("ICCM", MPU_REGION_ENTRY("ICCM",

4
boards/arc/nsim/nsim.dtsi
View file

@ -14,7 +14,7 @@
#endif #endif
#ifndef ICCM_SIZE #ifndef ICCM_SIZE
#define ICCM_SIZE DT_SIZE_K(512) #define ICCM_SIZE DT_SIZE_K(1024)
#endif #endif
#ifndef DCCM_ADDR #ifndef DCCM_ADDR
@ -22,7 +22,7 @@
#endif #endif
#ifndef DCCM_SIZE #ifndef DCCM_SIZE
#define DCCM_SIZE DT_SIZE_K(512) #define DCCM_SIZE DT_SIZE_K(1024)
#endif #endif
/ { / {

4
boards/arc/nsim/support/mdb_em.args
View file

@ -48,10 +48,10 @@
-dcache_feature=2 -dcache_feature=2
-icache=16384,32,2,a -icache=16384,32,2,a
-icache_feature=2 -icache_feature=2
-dccm_size=0x80000 -dccm_size=0x100000
-dccm_base=0x80000000 -dccm_base=0x80000000
-dccm_interleave -dccm_interleave
-iccm0_size=0x80000 -iccm0_size=0x100000
-iccm0_base=0x00000000 -iccm0_base=0x00000000
-Xpct_counters=8 -Xpct_counters=8
-dmac -dmac

4
boards/arc/nsim/support/nsim_em.props
View file

@ -55,10 +55,10 @@
nsim_isa_dc_feature_level=2 nsim_isa_dc_feature_level=2
icache=16384,32,2,a icache=16384,32,2,a
nsim_isa_ic_feature_level=2 nsim_isa_ic_feature_level=2
dccm_size=0x80000 dccm_size=0x100000
dccm_base=0x80000000 dccm_base=0x80000000
nsim_isa_dccm_interleave=1 nsim_isa_dccm_interleave=1
iccm0_size=0x80000 iccm0_size=0x100000
iccm0_base=0x00000000 iccm0_base=0x00000000
nsim_isa_pct_counters=8 nsim_isa_pct_counters=8
nsim_isa_dmac_option=1 nsim_isa_dmac_option=1

5
subsys/testsuite/coverage/coverage_ram.ld
View file

@ -64,10 +64,13 @@ __gcov_bss_size = __gcov_bss_end - __gcov_bss_start;
SECTION_PROLOGUE(_GCOV_BSS_SECTION_NAME, (NOLOAD),) SECTION_PROLOGUE(_GCOV_BSS_SECTION_NAME, (NOLOAD),)
{ {
MPU_MIN_SIZE_ALIGN MPU_MIN_SIZE_ALIGN
. = ALIGN(4);
__gcov_bss_start = .; __gcov_bss_start = .;
*(".bss.__gcov0.*"); *(".bss.__gcov0.*");
#ifdef CONFIG_USERSPACE
. = ALIGN(1 << LOG2CEIL(. - __gcov_bss_start));
#else
MPU_MIN_SIZE_ALIGN MPU_MIN_SIZE_ALIGN
#endif
__gcov_bss_end = .; __gcov_bss_end = .;
}GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) }GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)