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boards: nordic: Add support for nRF54H20 DK

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Add targets for the Application, Radio, and PPR cores in the nRF54H20
SoC on the nRF54H20 DK board.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit is contained in:
Andrzej Głąbek 2024-03-12 15:00:05 +01:00 • committed by Fabio Baltieri
commit d0ce78f230
20 changed files with 883 additions and 0 deletions
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boards/nordic/nrf54h20dk/Kconfig.nrf54h20dk Normal file
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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
config BOARD_NRF54H20DK
select SOC_NRF54H20_CPUAPP if BOARD_NRF54H20DK_NRF54H20_CPUAPP
select SOC_NRF54H20_CPURAD if BOARD_NRF54H20DK_NRF54H20_CPURAD
select SOC_NRF54H20_CPUPPR if BOARD_NRF54H20DK_NRF54H20_CPUPPR || \
BOARD_NRF54H20DK_NRF54H20_CPUPPR_RAM

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# SPDX-License-Identifier: Apache-2.0
if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP OR CONFIG_BOARD_NRF54H20DK_NRF54H20_CPURAD)
if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPURAD)
set(
JLINK_TOOL_OPT
"-jlinkscriptfile ${CMAKE_CURRENT_LIST_DIR}/support/nrf54h20_cpurad.JLinkScript"
)
endif()
board_runner_args(jlink "--device=CORTEX-M33" "--speed=4000" "--tool-opt=${JLINK_TOOL_OPT}")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
endif()

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boards/nordic/nrf54h20dk/board.yml Normal file
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board:
name: nrf54h20dk
vendor: nordic
socs:
- name: nrf54h20
variants:
- name: ram
cpucluster: cpuppr

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.. _nrf54h20dk_nrf54h20:
nRF54H20 DK
###########
Overview
********
.. note::
All software for the nRF54H20 SoC is experimental and hardware availability
is restricted to the participants in the limited sampling program.
The nRF54H20 DK is a single-board development kit for evaluation and development
on the Nordic nRF54H20 System-on-Chip (SoC).
The nRF54H20 is a multicore SoC with:
* an Arm Cortex-M33 core with DSP instructions, FPU, and Armv8-M Security
Extensions, running at up to 320 MHz, referred to as the **application core**
* an Arm Cortex-M33 core with DSP instructions, FPU, and Armv8-M Security
Extensions, running at up to 256 MHz, referred to as the **radio core**.
The ``nrf54h20dk/nrf54h20/cpuapp`` build target provides support for
the application core on the nRF54H20 SoC.
The ``nrf54h20dk/nrf54h20/cpurad`` build target provides support for
the radio core on the nRF54H20 SoC.
nRF54H20 SoC provides support for the following devices:
* :abbr:`ADC (Analog to Digital Converter)`
* CLOCK
* :abbr:`GPIO (General Purpose Input Output)`
* :abbr:`GRTC (Global real-time counter)`
* :abbr:`I2C (Inter-Integrated Circuit)`
* MRAM
* :abbr:`PWM (Pulse Width Modulation)`
* RADIO (Bluetooth Low Energy and 802.15.4)
* :abbr:`SPI (Serial Peripheral Interface)`
* :abbr:`UART (Universal asynchronous receiver-transmitter)`
* :abbr:`USB (Universal Serial Bus)`
* :abbr:`WDT (Watchdog Timer)`
Hardware
********
nRF54H20 DK has two crystal oscillators:
* High-frequency 32 MHz crystal oscillator (HFXO)
* Low-frequency 32.768 kHz crystal oscillator (LFXO)
Supported Features
==================
The ``nrf54h20dk/nrf54h20/cpuapp`` board configuration supports the following
hardware features:
+-----------+------------+----------------------+
| Interface | Controller | Driver/Component |
+===========+============+======================+
| GPIO | on-chip | gpio |
+-----------+------------+----------------------+
| GRTC | on-chip | system clock |
+-----------+------------+----------------------+
| I2C(M) | on-chip | i2c |
+-----------+------------+----------------------+
| SPI(M/S) | on-chip | spi |
+-----------+------------+----------------------+
| UART | on-chip | serial |
+-----------+------------+----------------------+
| WDT | on-chip | watchdog |
+-----------+------------+----------------------+
The ``nrf54h20dk/nrf54h20/cpurad`` board configuration supports the following
hardware features:
+-----------+------------+----------------------+
| Interface | Controller | Driver/Component |
+===========+============+======================+
| GPIO | on-chip | gpio |
+-----------+------------+----------------------+
| GRTC | on-chip | system clock |
+-----------+------------+----------------------+
| I2C(M) | on-chip | i2c |
+-----------+------------+----------------------+
| SPI(M/S) | on-chip | spi |
+-----------+------------+----------------------+
| UART | on-chip | serial |
+-----------+------------+----------------------+
| WDT | on-chip | watchdog |
+-----------+------------+----------------------+
Other hardware features have not been enabled yet for this board.
Connections and IOs
===================
LEDs
----
* LED1 (green) = P9.0
* LED2 (green) = P9.1
* LED3 (green) = P9.2
* LED4 (green) = P9.3
Push buttons
------------
* BUTTON1 = P0.8
* BUTTON2 = P0.9
* BUTTON3 = P0.10
* BUTTON4 = P0.11
* RESET (SW1)
Programming and Debugging
*************************
Applications for both the ``nrf54h20dk/nrf54h20/cpuapp`` and
``nrf54h20dk/nrf54h20/cpurad`` targets can be built, flashed,
and debugged in the usual way. See :ref:`build_an_application`
and :ref:`application_run` for more details on building and running.
Flashing
========
As an example, this section shows how to build and flash the :ref:`hello_world`
application.
Follow the instructions in the :ref:`nordic_segger` page to install
and configure all the necessary software. Further information can be
found in :ref:`nordic_segger_flashing`.
To build and program the sample to the nRF54H20 DK, complete the following steps:
1. Connect the nRF54H20 DK to your computer using the IMCU USB port on the DK.
#. Build the sample by running the following command:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: nrf54h20dk/nrf54h20/cpuapp
:goals: build flash
Testing the LEDs and buttons in the nRF54H20 DK
***********************************************
There are 2 samples that allow you to test that the buttons (switches) and LEDs
on the board are working properly with Zephyr:
* :zephyr:code-sample:`blinky`
* :zephyr:code-sample:`button`
You can build and flash the examples to make sure Zephyr is running correctly on
your board. The button and LED definitions can be found in
:zephyr_file:`boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts`.

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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
# Enable UART driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y

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boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf.dtsi Normal file
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/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/ {
ipc {
cpusec_cpuapp_ipc: ipc-1-2 {
compatible = "zephyr,ipc-icmsg";
status = "disabled";
mboxes = <&cpusec_bellboard 12>,
<&cpuapp_bellboard 0>;
};
cpusec_cpurad_ipc: ipc-1-3 {
compatible = "zephyr,ipc-icmsg";
status = "disabled";
mboxes = <&cpusec_bellboard 18>,
<&cpurad_bellboard 0>;
};
cpuapp_cpurad_ipc: ipc-2-3 {
status = "disabled";
mboxes = <&cpuapp_bellboard 18>,
<&cpurad_bellboard 12>;
};
cpuapp_cpuppr_ipc: ipc-2-13 {
compatible = "zephyr,ipc-icmsg";
status = "disabled";
mboxes = <&cpuapp_bellboard 13>,
<&cpuppr_vevif 12>;
};
};
};

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boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi Normal file
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/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/ {
reserved-memory {
cpuapp_ram0x_region: memory@2f000000 {
compatible = "nordic,owned-memory";
reg = <0x2f000000 DT_SIZE_K(260)>;
status = "disabled";
perm-read;
perm-write;
perm-secure;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2f000000 0x41000>;
cpusec_cpuapp_ipc_shm: memory@0 {
reg = <0x0 DT_SIZE_K(2)>;
};
cpuapp_cpusec_ipc_shm: memory@800 {
reg = <0x800 DT_SIZE_K(2)>;
};
cpuapp_data: memory@1000 {
reg = <0x1000 DT_SIZE_K(256)>;
};
};
cpurad_ram0x_region: memory@2f041000 {
compatible = "nordic,owned-memory";
reg = <0x2f041000 DT_SIZE_K(4)>;
status = "disabled";
perm-read;
perm-write;
perm-secure;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2f041000 0x1000>;
cpusec_cpurad_ipc_shm: memory@0 {
reg = <0x0 DT_SIZE_K(2)>;
};
cpurad_cpusec_ipc_shm: memory@800 {
reg = <0x800 DT_SIZE_K(2)>;
};
};
cpuapp_cpurad_ram0x_region: memory@2f0bf000 {
compatible = "nordic,owned-memory";
reg = <0x2f0bf000 DT_SIZE_K(4)>;
status = "disabled";
perm-read;
perm-write;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2f0bf000 0x1000>;
cpuapp_cpurad_ipc_shm: memory@0 {
reg = <0x0 DT_SIZE_K(2)>;
};
cpurad_cpuapp_ipc_shm: memory@800 {
reg = <0x800 DT_SIZE_K(2)>;
};
};
shared_ram20_region: memory@2f88f000 {
compatible = "nordic,owned-memory";
reg = <0x2f88f000 DT_SIZE_K(4)>;
status = "disabled";
perm-read;
perm-write;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2f88f000 0x1000>;
cpuapp_cpusys_ipc_shm: memory@ce0 {
reg = <0xce0 0x80>;
};
cpusys_cpuapp_ipc_shm: memory@d60 {
reg = <0xd60 0x80>;
};
cpurad_cpusys_ipc_shm: memory@e00 {
reg = <0xe00 0x80>;
};
cpusys_cpurad_ipc_shm: memory@e80 {
reg = <0xe80 0x80>;
};
};
cpuppr_ram3x_region: memory@2fc00000 {
compatible = "nordic,owned-memory";
reg = <0x2fc00000 DT_SIZE_K(64)>;
status = "disabled";
perm-read;
perm-write;
perm-execute;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2fc00000 0x10000>;
cpuppr_code_data: memory@0 {
reg = <0x0 DT_SIZE_K(62)>;
};
cpuapp_cpuppr_ipc_shm: memory@f800 {
reg = <0xf800 DT_SIZE_K(1)>;
};
cpuppr_cpuapp_ipc_shm: memory@fc00 {
reg = <0xfc00 DT_SIZE_K(1)>;
};
};
shared_ram3x_region: memory@2fc12000 {
compatible = "nordic,owned-memory";
reg = <0x2fc12000 DT_SIZE_K(8)>;
status = "disabled";
perm-read;
perm-write;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2fc12000 0x2000>;
cpuapp_dma_region: memory@e80 {
compatible = "zephyr,memory-region";
reg = <0xe80 DT_SIZE_K(4)>;
status = "disabled";
#memory-region-cells = <0>;
zephyr,memory-region = "DMA_RAM3x_APP";
};
cpurad_dma_region: memory@1e80 {
compatible = "zephyr,memory-region";
reg = <0x1e80 0x80>;
status = "disabled";
#memory-region-cells = <0>;
zephyr,memory-region = "DMA_RAM3x_RAD";
};
};
};
};
&mram1x {
cpurad_rx_partitions: cpurad-rx-partitions {
compatible = "nordic,owned-partitions", "fixed-partitions";
status = "disabled";
perm-read;
perm-execute;
perm-secure;
#address-cells = <1>;
#size-cells = <1>;
cpurad_slot0_partition: partition@66000 {
reg = <0x66000 DT_SIZE_K(256)>;
};
};
cpuapp_rx_partitions: cpuapp-rx-partitions {
compatible = "nordic,owned-partitions", "fixed-partitions";
status = "disabled";
perm-read;
perm-execute;
perm-secure;
#address-cells = <1>;
#size-cells = <1>;
cpuapp_slot0_partition: partition@a6000 {
reg = <0xa6000 DT_SIZE_K(512)>;
};
cpuppr_code_partition: partition@126000 {
reg = <0x126000 DT_SIZE_K(64)>;
};
};
};

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boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-pinctrl.dtsi Normal file
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/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
&pinctrl {
/omit-if-no-ref/ uart135_default: uart135_default {
group1 {
psels = <NRF_PSEL(UART_TX, 1, 11)>,
<NRF_PSEL(UART_RTS, 1, 9)>;
};
group2 {
bias-pull-up;
psels = <NRF_PSEL(UART_RX, 1, 10)>,
<NRF_PSEL(UART_CTS, 1, 7)>;
};
};
/omit-if-no-ref/ uart135_sleep: uart135_sleep {
group1 {
low-power-enable;
psels = <NRF_PSEL(UART_TX, 1, 11)>,
<NRF_PSEL(UART_RX, 1, 10)>,
<NRF_PSEL(UART_RTS, 1, 9)>,
<NRF_PSEL(UART_CTS, 1, 7)>;
};
};
/omit-if-no-ref/ uart136_default: uart136_default {
group1 {
psels = <NRF_PSEL(UART_TX, 2, 6)>,
<NRF_PSEL(UART_RTS, 2, 7)>;
};
group2 {
bias-pull-up;
psels = <NRF_PSEL(UART_RX, 2, 4)>,
<NRF_PSEL(UART_CTS, 2, 5)>;
};
};
/omit-if-no-ref/ uart136_sleep: uart136_sleep {
group1 {
low-power-enable;
psels = <NRF_PSEL(UART_TX, 2, 6)>,
<NRF_PSEL(UART_RX, 2, 4)>,
<NRF_PSEL(UART_RTS, 2, 7)>,
<NRF_PSEL(UART_CTS, 2, 5)>;
};
};
};

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/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <nordic/nrf54h20_cpuapp.dtsi>
#include "nrf54h20dk_nrf54h20-memory_map.dtsi"
#include "nrf54h20dk_nrf54h20-ipc_conf.dtsi"
#include "nrf54h20dk_nrf54h20-pinctrl.dtsi"
/delete-node/ &cpusec_cpurad_ipc;
/ {
compatible = "nordic,nrf54h20dk_nrf54h20-cpuapp";
model = "Nordic nRF54H20 DK nRF54H20 Application MCU";
chosen {
zephyr,console = &uart136;
zephyr,code-partition = &cpuapp_slot0_partition;
zephyr,flash = &mram1x;
zephyr,sram = &cpuapp_data;
};
aliases {
led0 = &led0;
led1 = &led1;
led2 = &led2;
led3 = &led3;
sw0 = &button0;
sw1 = &button1;
sw2 = &button2;
sw3 = &button3;
};
buttons {
compatible = "gpio-keys";
button0: button_0 {
gpios = <&gpio0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button 0";
zephyr,code = <INPUT_KEY_0>;
};
button1: button_1 {
gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button 1";
zephyr,code = <INPUT_KEY_1>;
};
button2: button_2 {
gpios = <&gpio0 10 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button 2";
zephyr,code = <INPUT_KEY_2>;
};
button3: button_3 {
gpios = <&gpio0 11 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button 3";
zephyr,code = <INPUT_KEY_3>;
};
};
leds {
compatible = "gpio-leds";
led0: led_0 {
gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>;
label = "Green LED 0";
};
led1: led_1 {
gpios = <&gpio9 1 GPIO_ACTIVE_HIGH>;
label = "Green LED 1";
};
led2: led_2 {
gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>;
label = "Green LED 2";
};
led3: led_3 {
gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>;
label = "Green LED 3";
};
};
};
&cpuapp_ram0x_region {
status = "okay";
};
&shared_ram3x_region {
status = "okay";
};
&cpuapp_bellboard {
interrupts = <96 NRF_DEFAULT_IRQ_PRIORITY>;
interrupt-names = "irq0";
/* irq0: 0: cpuapp-cpusec, 13: cpuapp-cpuppr, 18: cpuapp-cpurad */
nordic,interrupt-mapping = <0x00042001 0>;
};
&cpusec_cpuapp_ipc {
mbox-names = "tx", "rx";
tx-region = <&cpuapp_cpusec_ipc_shm>;
rx-region = <&cpusec_cpuapp_ipc_shm>;
};
&cpuapp_cpurad_ipc {
compatible = "zephyr,ipc-icmsg-me-initiator";
mbox-names = "rx", "tx";
tx-region = <&cpuapp_cpurad_ipc_shm>;
rx-region = <&cpurad_cpuapp_ipc_shm>;
};
&cpuapp_cpuppr_ipc {
mbox-names = "rx", "tx";
tx-region = <&cpuapp_cpuppr_ipc_shm>;
rx-region = <&cpuppr_cpuapp_ipc_shm>;
};
&cpuapp_dma_region {
status = "okay";
};
&cpuapp_rx_partitions {
status = "okay";
};
&cpuppr_vpr {
execution-memory = <&cpuppr_code_partition>;
};
&gpiote130 {
status = "okay";
owned-channels = <0 1 2 3 4 5 6 7>;
};
&gpio0 {
status = "okay";
};
&gpio9 {
status = "okay";
};
&grtc {
status = "okay";
child-owned-channels = <5 6>;
nonsecure-channels = <5 6>;
owned-channels = <4 5 6>;
};
&uart135 {
current-speed = <115200>;
pinctrl-0 = <&uart135_default>;
pinctrl-1 = <&uart135_sleep>;
pinctrl-names = "default", "sleep";
};
&uart136 {
status = "okay";
memory-regions = <&cpuapp_dma_region>;
current-speed = <115200>;
pinctrl-0 = <&uart136_default>;
pinctrl-1 = <&uart136_sleep>;
pinctrl-names = "default", "sleep";
};

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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
identifier: nrf54h20dk/nrf54h20/cpuapp
name: nRF54H20-DK-nRF54H20-Application
type: mcu
arch: arm
toolchain:
- gnuarmemb
- xtools
- zephyr
ram: 256
flash: 512
supported:
- gpio

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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
CONFIG_USE_DT_CODE_PARTITION=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# MPU-based null-pointer dereferencing detection cannot be applied
# as the (0x0 - 0x400) region is unmapped for this target.
CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
# Enable cache
CONFIG_CACHE_MANAGEMENT=y
CONFIG_EXTERNAL_CACHE=y
# Enable GPIO
CONFIG_GPIO=y

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/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <nordic/nrf54h20_cpuppr.dtsi>
#include "nrf54h20dk_nrf54h20-memory_map.dtsi"
#include "nrf54h20dk_nrf54h20-ipc_conf.dtsi"
#include "nrf54h20dk_nrf54h20-pinctrl.dtsi"
/delete-node/ &cpuapp_cpurad_ipc;
/delete-node/ &cpusec_cpuapp_ipc;
/delete-node/ &cpusec_cpurad_ipc;
/ {
compatible = "nordic,nrf54h20dk_nrf54h20-cpuppr";
model = "Nordic nRF54H20 DK nRF54H20 Peripheral Processor MCU";
#address-cells = <1>;
#size-cells = <1>;
chosen {
zephyr,console = &uart135;
zephyr,code-partition = &cpuppr_code_partition;
zephyr,flash = &mram1x;
zephyr,sram = &cpuppr_code_data;
};
};
&cpuapp_cpuppr_ipc {
mbox-names = "tx", "rx";
tx-region = <&cpuppr_cpuapp_ipc_shm>;
rx-region = <&cpuapp_cpuppr_ipc_shm>;
};
&grtc {
status = "okay";
owned-channels = <5>;
};
&uart135 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart135_default>;
pinctrl-1 = <&uart135_sleep>;
pinctrl-names = "default", "sleep";
};
&uart136 {
current-speed = <115200>;
pinctrl-0 = <&uart136_default>;
pinctrl-1 = <&uart136_sleep>;
pinctrl-names = "default", "sleep";
};

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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
identifier: nrf54h20dk/nrf54h20/cpuppr
name: nRF54H20-DK-nRF54H20-PPR
type: mcu
arch: riscv
toolchain:
- zephyr
ram: 62
flash: 64
supported:
- gpio

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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
CONFIG_USE_DT_CODE_PARTITION=y

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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
identifier: nrf54h20dk/nrf54h20/cpuppr/ram
name: nRF54H20-DK-nRF54H20-PPR-RAM
type: mcu
arch: riscv
toolchain:
- zephyr
ram: 62
flash: 62
supported:
- gpio

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boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_ram_defconfig Normal file
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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
CONFIG_XIP=n

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boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts Normal file
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/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <nordic/nrf54h20_cpurad.dtsi>
#include "nrf54h20dk_nrf54h20-memory_map.dtsi"
#include "nrf54h20dk_nrf54h20-ipc_conf.dtsi"
#include "nrf54h20dk_nrf54h20-pinctrl.dtsi"
/delete-node/ &cpuapp_cpuppr_ipc;
/delete-node/ &cpusec_cpuapp_ipc;
/ {
compatible = "nordic,nrf54h20dk_nrf54h20-cpurad";
model = "Nordic nRF54H20 DK nRF54H20 Radio MCU";
chosen {
zephyr,console = &uart135;
zephyr,code-partition = &cpurad_slot0_partition;
zephyr,flash = &mram1x;
zephyr,sram = &cpurad_ram0;
};
};
&shared_ram3x_region {
status = "okay";
};
&cpurad_bellboard {
interrupts = <96 NRF_DEFAULT_IRQ_PRIORITY>;
interrupt-names = "irq0";
/* irq0: 0: cpurad-cpusec, 12: cpurad-cpuapp */
nordic,interrupt-mapping = <0x00001001 0>;
};
&cpusec_cpurad_ipc {
mbox-names = "tx", "rx";
tx-region = <&cpurad_cpusec_ipc_shm>;
rx-region = <&cpusec_cpurad_ipc_shm>;
};
&cpuapp_cpurad_ipc {
compatible = "zephyr,ipc-icmsg-me-follower";
mbox-names = "tx", "rx";
tx-region = <&cpurad_cpuapp_ipc_shm>;
rx-region = <&cpuapp_cpurad_ipc_shm>;
};
&cpurad_dma_region {
status = "okay";
};
&cpurad_rx_partitions {
status = "okay";
};
&grtc {
status = "okay";
child-owned-channels = <8 9 10 11 12>;
interrupts = <109 NRF_DEFAULT_IRQ_PRIORITY>,
<108 NRF_DEFAULT_IRQ_PRIORITY>;
nonsecure-channels = <8 9 10 11 12>;
owned-channels = <7 8 9 10 11 12 13 14>;
};
&uart135 {
status = "okay";
memory-regions = <&cpurad_dma_region>;
current-speed = <115200>;
pinctrl-0 = <&uart135_default>;
pinctrl-1 = <&uart135_sleep>;
pinctrl-names = "default", "sleep";
};
&uart136 {
current-speed = <115200>;
pinctrl-0 = <&uart136_default>;
pinctrl-1 = <&uart136_sleep>;
pinctrl-names = "default", "sleep";
};

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boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.yaml Normal file
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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
identifier: nrf54h20dk/nrf54h20/cpurad
name: nRF54H20-DK-nRF54H20-Radio
type: mcu
arch: arm
toolchain:
- gnuarmemb
- xtools
- zephyr
ram: 192
flash: 256
supported:
- gpio

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boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_defconfig Normal file
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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
CONFIG_USE_DT_CODE_PARTITION=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# MPU-based null-pointer dereferencing detection cannot be applied
# as the (0x0 - 0x400) region is unmapped for this target.
CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
# Enable cache
CONFIG_CACHE_MANAGEMENT=y
CONFIG_EXTERNAL_CACHE=y

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boards/nordic/nrf54h20dk/support/nrf54h20_cpurad.JLinkScript Normal file
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void ConfigTargetSettings(void) {
JLINK_ExecCommand("CORESIGHT_AddAP = Index=1 Type=AHB-AP");
CORESIGHT_IndexAHBAPToUse = 1;
}