diff --git a/dts/arm/st/l4/stm32l4.dtsi b/dts/arm/st/l4/stm32l4.dtsi
index 89850fbfc07..e4eb3f7725f 100644
--- a/dts/arm/st/l4/stm32l4.dtsi
+++ b/dts/arm/st/l4/stm32l4.dtsi
@@ -331,6 +331,18 @@
 			status = "disabled";
 			label = "DMA_2";
 		};
+
+		lptim1: timers@40007c00 {
+			compatible = "st,stm32-timers";
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40007c00 0x400>;
+			interrupts = <65 0>;
+			interrupt-names = "wakeup";
+			status = "disabled";
+			label = "LPTIM_1";
+		};
 	};
 };
 
diff --git a/soc/arm/st_stm32/stm32l4/dts_fixup.h b/soc/arm/st_stm32/stm32l4/dts_fixup.h
index fa9fc9e512b..ba068ead3d5 100644
--- a/soc/arm/st_stm32/stm32l4/dts_fixup.h
+++ b/soc/arm/st_stm32/stm32l4/dts_fixup.h
@@ -328,4 +328,11 @@
 #define DT_ADC_1_CLOCK_BITS		DT_ST_STM32_ADC_50040000_CLOCK_BITS_0
 #define DT_ADC_1_CLOCK_BUS		DT_ST_STM32_ADC_50040000_CLOCK_BUS_0
 
+#define DT_LPTIM_1_BASE_ADDRESS	DT_ST_STM32_TIMERS_40007C00_BASE_ADDRESS
+#define DT_LPTIM_1_IRQ		DT_ST_STM32_TIMERS_40007C00_IRQ_0
+#define DT_LPTIM_1_IRQ_PRI	DT_ST_STM32_TIMERS_40007C00_IRQ_0_PRIORITY
+#define DT_LPTIM_1_NAME		DT_ST_STM32_TIMERS_40007C00_LABEL
+#define DT_LPTIM_1_CLOCK_BITS	DT_ST_STM32_TIMERS_40007C00_CLOCK_BITS_0
+#define DT_LPTIM_1_CLOCK_BUS	DT_ST_STM32_TIMERS_40007C00_CLOCK_BUS_0
+
 /* End of SoC Level DTS fixup file */
diff --git a/soc/arm/st_stm32/stm32l4/soc.h b/soc/arm/st_stm32/stm32l4/soc.h
index 4a79f2ed6a7..d067ee19d9d 100644
--- a/soc/arm/st_stm32/stm32l4/soc.h
+++ b/soc/arm/st_stm32/stm32l4/soc.h
@@ -94,6 +94,11 @@
 #include <stm32l4xx_ll_dma.h>
 #endif
 
+#ifdef CONFIG_STM32_LPTIM_TIMER
+#include <stm32l4xx_ll_lptim.h>
+#include <stm32l4xx_ll_system.h>
+#endif
+
 #endif /* !_ASMLANGUAGE */
 
 #endif /* _STM32L4X_SOC_H_ */