riscv32: move riscv privileged architecture specifics within a common header file

Added a riscv-privilege.h header file that contains common
definitions for all riscv SOCs supporting the riscv
privileged architecture specification.

This shall ease addition of future riscv SOCs supporting
the riscv privileged architecture spec.

Change-Id: I5714bf70eeda738a25967ed26d3d0d2aaa0c9989
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>

arch/riscv32/Makefile

@@ -15,5 +15,6 @@ KBUILD_CFLAGS += $(soc-cflags)
 KBUILD_CXXFLAGS += $(soc-cxxflags)
 KBUILD_AFLAGS += $(soc-aflags)
 
-soc_ld_include := -I$(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/
+soc_ld_include := -I$(srctree)/arch/$(ARCH)/soc \
+		  -I$(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/
 EXTRA_LINKER_CMD_OPT += $(soc_ld_include)

arch/riscv32/core/fatal.c

@@ -193,7 +193,7 @@ FUNC_NORETURN void _Fault(const NANO_ESF *esf)
 
 	__asm__ volatile("csrr %0, mcause" : "=r" (mcause));
 
-	mcause &= SOC_MCAUSE_IRQ_MASK;
+	mcause &= SOC_MCAUSE_EXP_MASK;
 
 	PRINTK("Exception cause %s (%d)\n", cause_str(mcause), (int)mcause);
 

arch/riscv32/core/irq_manage.c

@@ -16,7 +16,7 @@ void _irq_spurious(void *unused)
 
 	__asm__ volatile("csrr %0, mcause" : "=r" (mcause));
 
-	mcause &= SOC_MCAUSE_IRQ_MASK;
+	mcause &= SOC_MCAUSE_EXP_MASK;
 
 	printk("Spurious interrupt detected! IRQ: %d\n", (int)mcause);
 

arch/riscv32/core/isr.S

@@ -141,7 +141,7 @@ SECTION_FUNC(exception.entry, __irq_wrapper)
 	 * to report the exception.
 	 */
 	csrr t0, mcause
-	li t2, SOC_MCAUSE_IRQ_MASK
+	li t2, SOC_MCAUSE_EXP_MASK
 	and t0, t0, t2
 	li t1, SOC_MCAUSE_ECALL_EXP
 
@@ -235,7 +235,7 @@ call_irq:
 
 	/* Get IRQ causing interrupt */
 	csrr a0, mcause
-	li t0, SOC_MCAUSE_IRQ_MASK
+	li t0, SOC_MCAUSE_EXP_MASK
 	and a0, a0, t0
 
 	/*

arch/riscv32/include/kernel_event_logger_arch.h

@@ -32,7 +32,7 @@ static inline int _sys_current_irq_key_get(void)
 
 	__asm__ volatile("csrr %0, mcause" : "=r" (mcause));
 
-	mcause &= SOC_MCAUSE_IRQ_MASK;
+	mcause &= SOC_MCAUSE_EXP_MASK;
 
 	return mcause;
 }

arch/riscv32/soc/pulpino/soc.h

@@ -52,7 +52,7 @@
 #define SOC_MSTATUS_DEF_RESTORE    SOC_MSTATUS_IEN
 
 /* SOC-specific MCAUSE bitfields */
-#define SOC_MCAUSE_IRQ_MASK        0x1F           /* Exception code Mask */
+#define SOC_MCAUSE_EXP_MASK        0x1F           /* Exception code Mask */
 #define SOC_MCAUSE_ECALL_EXP       PULP_ECALL_EXP /* ECALL exception number */
 
 /* SOC-Specific EXIT ISR command */

arch/riscv32/soc/pulpino/soc_irq.S

@@ -99,7 +99,7 @@ SECTION_FUNC(exception.other, __soc_handle_irq)
 SECTION_FUNC(exception.other, __soc_is_irq)
 	/* Get exception number from the mcause CSR register. */
 	csrr t0, mcause
-	andi t0, t0, SOC_MCAUSE_IRQ_MASK
+	andi t0, t0, SOC_MCAUSE_EXP_MASK
 
 	/* if IRQ number < PULP_MIN_IRQ, not interrupt */
 	li t1, PULP_MIN_IRQ

arch/riscv32/soc/riscv-privilege.h

@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file configuration macros for riscv SOCs supporting the riscv
+ *       privileged architecture specification
+ */
+
+#ifndef __RISCV_PRIVILEGE_H_
+#define __RISCV_PRIVILEGE_H_
+
+/* IRQ numbers */
+#define RISCV_MACHINE_SOFT_IRQ       3  /* Machine Software Interrupt */
+#define RISCV_MACHINE_TIMER_IRQ      7  /* Machine Timer Interrupt */
+#define RISCV_MACHINE_EXT_IRQ        11 /* Machine External Interrupt */
+
+/* Exception numbers */
+#define RISCV_MACHINE_ECALL_EXP      11 /* Machine ECALL instruction */
+
+/*
+ * SOC-specific MSTATUS related info
+ */
+/* MSTATUS register to save/restore upon interrupt/exception/context switch */
+#define SOC_MSTATUS_REG              mstatus
+
+#define SOC_MSTATUS_IEN              (1 << 3) /* Machine Interrupt Enable bit */
+
+/* Previous Privilege Mode - Machine Mode */
+#define SOC_MSTATUS_MPP_M_MODE       (3 << 11)
+/* Interrupt Enable Bit in Previous Privilege Mode */
+#define SOC_MSTATUS_MPIE             (1 << 7)
+
+/*
+ * Default MSTATUS register value to restore from stack
+ * upon scheduling a thread for the first time
+ */
+#define SOC_MSTATUS_DEF_RESTORE      (SOC_MSTATUS_MPP_M_MODE | SOC_MSTATUS_MPIE)
+
+
+/* SOC-specific MCAUSE bitfields */
+/* Interrupt Mask */
+#define SOC_MCAUSE_IRQ_MASK          (1 << 31)
+/* Exception code Mask */
+#define SOC_MCAUSE_EXP_MASK          0x7FFFFFFF
+/* ECALL exception number */
+#define SOC_MCAUSE_ECALL_EXP         RISCV_MACHINE_ECALL_EXP
+
+/* SOC-Specific EXIT ISR command */
+#define SOC_ERET                     mret
+
+#endif /* __RISCV_PRIVILEGE_H_ */

arch/riscv32/soc/riscv32-qemu/Makefile

@@ -1 +1,2 @@
-soc-cflags := -I/$(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/
+soc-cflags := -I/$(srctree)/arch/$(ARCH)/soc/ \
+	      -I/$(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/

arch/riscv32/soc/riscv32-qemu/soc.h

@@ -11,46 +11,10 @@
 #ifndef __RISCV32_QEMU_SOC_H_
 #define __RISCV32_QEMU_SOC_H_
 
+#include <riscv-privilege.h>
+
 #include <misc/util.h>
 
-/* CSR Registers */
-#define RISCV_QEMU_MSTATUS               mstatus /* Machine Status Register */
-
-/* IRQ numbers */
-#define RISCV_MACHINE_TIMER_IRQ          7  /* Machine Timer Interrupt */
-
-/* Exception numbers */
-#define RISCV_QEMU_ECALL_EXP             11 /* ECALL Instruction */
-
-/*
- * SOC-specific MSTATUS related info
- */
-/* MSTATUS register to save/restore upon interrupt/exception/context switch */
-#define SOC_MSTATUS_REG              RISCV_QEMU_MSTATUS
-
-#define SOC_MSTATUS_IEN              (1 << 3) /* Machine Interrupt Enable bit */
-
-/* Previous Privilege Mode - Machine Mode */
-#define SOC_MSTATUS_MPP_M_MODE       (3 << 11)
-/* Interrupt Enable Bit in Previous Privilege Mode */
-#define SOC_MSTATUS_MPIE             (1 << 7)
-
-/*
- * Default MSTATUS register value to restore from stack
- * upon scheduling a thread for the first time
- */
-#define SOC_MSTATUS_DEF_RESTORE      (SOC_MSTATUS_MPP_M_MODE | SOC_MSTATUS_MPIE)
-
-
-/* SOC-specific MCAUSE bitfields */
-/* Exception code Mask */
-#define SOC_MCAUSE_IRQ_MASK          0x7FFFFFFF
-/* ECALL exception number */
-#define SOC_MCAUSE_ECALL_EXP         RISCV_QEMU_ECALL_EXP
-
-/* SOC-Specific EXIT ISR command */
-#define SOC_ERET                     mret
-
 /* UART configuration */
 #define RISCV_QEMU_UART_BASE         0x40002000
 

arch/riscv32/soc/riscv32-qemu/soc_irq.S

@@ -36,7 +36,7 @@ SECTION_FUNC(exception.other, __soc_handle_irq)
 SECTION_FUNC(exception.other, __soc_is_irq)
 	/* Get exception number from the mcause CSR register. */
 	csrr t0, mcause
-	li t1, SOC_MCAUSE_IRQ_MASK
+	li t1, SOC_MCAUSE_EXP_MASK
 	and t0, t0, t1
 
 	/* if IRQ number != RISCV_MACHINE_TIMER_IRQ, not interrupt */